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? 2006?2011 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data the mpc8347ea powerquicc ii pro is a next generation powerquicc ii integrated host processor. the mpc8347ea contains a proce ssor core built on power architecture? technology with system logic for networking, storage, and general-purpos e embedded applications. for functional characteristics of the processor, refer to the mpc8349ea powerquicc ii pro integrated host processor family reference manual . to locate published errata or upda tes for this document, refer to the mpc8347ea product summary page on our website, as listed on the back cover of this document, or contact your local freescale sales office. document number: mpc8347eaec rev. 12, 09/2011 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 6 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 4. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 16 7. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8. ethernet: three-speed ethernet, mii management . 23 9. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 14. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 16. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 17. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 18. package and pin listings . . . . . . . . . . . . . . . . . . . . . 54 19. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 20. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21. system design information . . . . . . . . . . . . . . . . . . . 91 22. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 94 23. document revision history . . . . . . . . . . . . . . . . . . . 96 mpc8347ea powerquicc ii pro integrated host processor hardware specifications
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 2 freescale semiconductor overview note the information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending in a or b). for information on revision 1.1 silic on and earlier versions, see the mpc8347e powerquicc ii pro integrated host processor hardware specifications. see section 22.1, ?part numbers fully addressed by this document,? for silicon revision le vel determination. 1 overview this section provides a high-level overview of the device features. figure 1 shows the major functional units within the mpc8347ea. figure 1. mpc8347ea block diagram major features of the device are as follows: ? embedded powerpc e300 processor core; operates at up to 667 mhz ? high-performance, superscalar processor core ? floating-point, integer, lo ad/store, system register, and branch processing units ? 32-kbyte instruction cach e, 32-kbyte data cache ? lockable portion of l1 cache ? dynamic power management ? software-compatible with the other freescale processor families that implement power architecture technology ? double data rate, ddr1/ddr 2 sdram memory controller ? programmable timing support ing ddr1 and ddr2 sdram ? 32- or 64-bit data interface, up to 400 mhz data rate for tbga, 266 mhz for pbga duart dual i 2 c timers gpio security interrupt controller dual role high-speed local bus ddr sdram controller host 32kb d-cache e300 core 32kb i-cache usb 2.0 10/100/1000 seq pci dma ethernet 10/100/1000 ethernet
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 3 overview ? up to four physical banks (chip selects), each bank up to 1 gbyte independently addressable ? dram chip configurations from 64 mbit s to 1 gbit with 8/16 data ports ? full error checking and correction (ecc) support ? support for up to 16 simultaneous open pages (up to 32 pages for ddr2) ? contiguous or discontiguous memory mapping ? read-modify-write support ? sleep-mode support for sdram self refresh ? auto refresh ? on-the-fly power management using cke ? registered dimm support ? 2.5-v sstl2 compatible i/o for ddr 1, 1.8-v sstl2 compatible i/o for ddr2 ? dual three-speed (10/100/1000) et hernet controllers (tsecs) ? dual controllers designed to comply with ieee 802.3?, 802.3u?, 820.3x?, 802.3z?, 802.3ac? standards ? ethernet physical interfaces: ? 1000 mbps ieee std. 802.3 gmii/rgmii, ieee std. 802.3z tbi/rtbi, full-duplex ? 10/100 mbps ieee std. 802.3 mii full- and half-duplex ? buffer descriptors are backward-compa tible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? internal 2-kbyte transmit and 2-k byte receive fifos per tsec module ? mii management interface for control and status ? programmable crc ge neration and checking ? pci interface ? designed to comply with pci specification revision 2.3 ? data bus width: ? 32-bit data pci interface operating at up to 66 mhz ? pci 3.3-v compatible ? pci host bridge capabilities ? pci agent mode on pci interface ? pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses and support for delayed read transactions ? posting of processor-to-pci and pci-to-memory writes ? on-chip arbitration suppor ting five masters on pci ? accesses to all pci address spaces ? parity supported ? selectable hardware-enforced coherency
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 4 freescale semiconductor overview ? address translation units for addres s mapping between hos t and peripheral ? dual address cycle for target ? internal configuration regi sters accessible from pci ? security engine is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, ieee std. 802.11i?, iscsi, and ike processi ng. the security engine contains four crypto-channels, a controller, and a set of crypto execution units (eus): ? public key execution unit (pkeu) : ? rsa and diffie-hellman algorithms ? programmable field size up to 2048 bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standard (des) execution unit (deu) ? des and 3des algorithms ? two key (k1, k2) or three key (k1, k2, k3) for 3des ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rijndael symmetric-key cipher ? key lengths of 128, 192, and 256 bits ? ecb, cbc, ccm, and counter (ctr) modes ? xor parity generation acceler ator for raid applications ? arc four execution unit (afeu) ? stream cipher compatible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160-, 224-, or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? random number generator (rng) ? four crypto-channels, each supporting multi-command descriptor chains ? static and/or dynamic assignm ent of crypto-execution units th rough an integrated controller ? buffer size of 256 bytes for each execution uni t, with flow control for large data sizes ? universal serial bus (usb) dual role controller ? usb on-the-go mode with bot h device and host functionality ? complies with usb specification rev. 2.0 ? can operate as a stand-alone usb device ? one upstream facing port ? six programmable usb endpoints
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 5 overview ? can operate as a stand-alone usb host controller ? usb root hub with one downstream-facing port ? enhanced host controller in terface (ehci) compatible ? high-speed (480 mbps), full -speed (12 mbps), and lo w-speed (1.5 mbps) operations ? external phy with utmi, serial a nd utmi+ low-pin in terface (ulpi) ? universal serial bus (usb ) multi-port host controller ? can operate as a stand-alone usb host controller ? usb root hub with one or two downstream-facing ports ? enhanced host controller in terface (ehci) compatible ? complies with usb specification rev. 2.0 ? high-speed (480 mbps), full -speed (12 mbps), and low-speed (1.5 mbps) operations ? direct connection to a high-speed device without an external hub ? external phy with serial and low-pin count (ulpi) interfaces ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 133 mhz ? eight chip selects for eight external slaves ? up to eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controll ed by an on-chip memory controller ? three protocol engines on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user-programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with conf igurable bus width (8-, 16-, or 32-bit) ? programmable interrupt controller (pic) ? functional and programming compatibility with the mpc8260 inte rrupt controller ? support for 8 external and 35 inte rnal discrete interrupt sources ? support for 1 external (optional) and 7 in ternal machine checkstop interrupt sources ? programmable highest priority request ? four groups of interrupts with programmable priority ? external and internal interrupt s directed to host processor ? redirects interrupts to external inta pin in core disable mode. ? unique vector number fo r each interrupt source ? dual industry-standard i 2 c interfaces ? two-wire interface ? multiple master support ? master or slave i 2 c mode support
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 6 freescale semiconductor electrical characteristics ? on-chip digital filtering rejects spikes on the bus ? system initialization data optionally loaded from i 2 c-1 eprom by boot se quencer embedded hardware ? dma controller ? four independent virtual channels ? concurrent execution across multiple channels with pr ogrammable bandwidth control ? handshaking (external control) si gnals for all channels: dma_dreq [0:3], dma_dack [0:3], dma_ddone [0:3] ? all channels accessible to local core and remote pci masters ? misaligned transfer capability ? data chaining and direct mode ? interrupt on completed segment and chain ? duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? serial peripheral interface (s pi) for master or slave ? general-purpose parallel i/o (gpio) ? 52 parallel i/o pins multip lexed on various chip interfaces ? system timers ? periodic interrupt timer ? real-time clock ? software watchdog timer ? eight general-purpose timers ? designed to comply with ieee std. 1149.1?, jtag boundary scan ? integrated pci bus and sdram clock generation 2 electrical characteristics this section provides the ac and dc electrical sp ecifications and thermal characteristics for the mpc8347ea. the device is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, c onditions, and other characteristics.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 7 electrical characteristics 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 parameter symbol max value unit notes core supply voltage v dd ?0.3 to 1.32 (1.36 max for 667-mhz core frequency) v? pll supply voltage av dd ?0.3 to 1.32 (1.36 max for 667-mhz core frequency) v? ddr and ddr2 dram i/o voltage gv dd ?0.3 to 2.75 ?0.3 to 1.98 v? three-speed ethernet i/o, mii management voltage lv dd ?0.3 to 3.63 v ? pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v ? input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 5 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4, 5 local bus, duart, clkin, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 3, 5 pci ov in ?0.3 to (ov dd + 0.3) v 6 storage temperature range t stg ?55 to 150 c? notes: 1 functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresse s beyond those listed may affect device reliability or cause permanent damage to the device. 2 caution: mv in must not exceed gv dd by more than 0.3 v. this limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3 caution: ov in must not exceed ov dd by more than 0.3 v. this limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4 caution: lv in must not exceed lv dd by more than 0.3 v. this limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5 (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 6 ovin on the pci interface can overshoot/undershoot according to the pci electrical specific ation for 3.3-v operation, as shown in figure 3 .
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 8 freescale semiconductor electrical characteristics 2.1.2 power supply voltage specification table 2 provides the recommended operating conditions fo r the mpc8347ea. note that the values in table 2 are the recommended and tested operating c onditions. proper device operation outside these conditions is not guaranteed. figure 2 shows the undershoot and overshoot voltages at the in terfaces of the mpc8347ea. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd table 2. recommended operating conditions parameter symbol recommended value unit notes core supply voltage for 667-mhz core frequency v dd 1.3 v 60 mv v 1 core supply voltage v dd 1.2 v 60 mv v 1 pll supply voltage for 667-mhz core frequency av dd 1.3 v 60 mv v 1 pll supply voltage av dd 1.2 v 60 mv v 1 ddr and ddr2 dram i/o voltage gv dd 2.5 v 125 mv 1.8 v 90 mv v? three-speed ethernet i/o supply voltage lv dd1 3.3 v 330 mv 2.5 v 125 mv v? three-speed ethernet i/o supply voltage lv dd2 3.3 v 330 mv 2.5 v 125 mv v? pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 330 mv v ? note: 1 gv dd , lv dd , ov dd , av dd , and v dd must track each other and must vary in the same direction?either in the positive or negative direction. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t interface 1 1. t interface refers to the clock period associated with the bus clock interface. v ih v il note:
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 9 electrical characteristics figure 3 shows the undershoot and over shoot voltage of the pci inte rface of the mpc8347ea for the 3.3-v signals, respectively. figure 3. maximum ac waveforms on pci interface for 3.3-v signaling 2.1.3 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.2 power sequencing this section details the power sequenc ing considerations for the mpc8347ea. 2.2.1 power-up sequencing mpc8347eadoes not require th e core supply voltage (v dd and av dd ) and i/o supply voltages (gv dd , lv dd , and ov dd ) to be applied in any part icular order. during the pow er ramp up, before the power table 3. output drive capability driver type output impedance ( ) supply voltag e local bus interface utilities signals 40 ov dd = 3.3 v pci signals (not including pci output clocks) 25 pci output clocks (including pci_sync_out) 40 ddr signal 18 gv dd = 2.5 v ddr2 signal 18 36 (half-strength mode) gv dd = 1.8 v tsec/10/100 signals 40 lv dd = 2.5/3.3 v duart, system control, i 2 c, jtag, usb 40 ov dd = 3.3 v gpio signals 40 ov dd = 3.3 v, lv dd = 2.5/3.3 v undervoltage waveform overvoltage waveform 11 ns (min) +7.1 v 7.1 v p-to-p (min) 4 ns (max) ?3.5 v 7.1 v p-to-p (min) 62.5 ns +3.6 v 0 v 4 ns (max)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 10 freescale semiconductor power characteristics supplies are stable and if the i/o voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current from 3a to 5a. in order to avoid actively driving the i/o pi ns and to eliminate excessive current draw, apply the core voltage (v dd ) before the i/o voltage (gv dd , lv dd , and ov dd ) and assert poreset before the power supplies fully ramp up. in the case where the core voltage is app lied first, the core voltage supply must rise to 90% of its nominal value before the i/o supplies reach 0.7 v, see figure 4 . figure 4. power sequencing example i/o voltage supplies (gv dd , lv dd , and ov dd ) do not have any or dering requirements wi th respect to one another. 3 power characteristics the estimated typical power dissipation for the mpc8347ea device is shown in table 4 . table 4. mpc8347ea power dissipation 1 core frequency (mhz) csb frequency (mhz) typical at t j = 65 typical 2 , 3 maximum 4 unit pbga 266 266 1.3 1.6 1.8 w 133 1.1 1.4 1.6 w 400 266 1.5 1.9 2.1 w 133 1.4 1.7 1.9 w 400 200 1.5 1.8 2.0 w 100 1.3 1.7 1.9 w i/o voltage (gv dd , lv dd , ov dd ) core voltage (v dd , av dd ) 90% 0.7 v time voltage
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 11 power characteristics tbga 333 333 2.0 3.0 3.2 w 166 1.8 2.8 2.9 w 400 266 2.1 3.0 3.3 w 133 1.9 2.9 3.1 w 450 300 2.3 3.2 3.5 w 150 2.1 3.0 3.2 w 500 333 2.4 3.3 3.6 w 166 2.2 3.1 3.4 w 533 266 2.4 3.3 3.6 w 133 2.2 3.1 3.4 w 667 5,6 333 3.5 4.6 5 w 1 the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . for i/o power values, see ta b l e 5 . 2 typical power is based on a voltage of v dd = 1.2 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 3 thermal solutions may need to design to a value higher than typical power based on the end application, t a target, and i/o power. 4 maximum power is based on a voltage of v dd = 1.2 v, worst case process, a junction temperature of t j = 105 c, and an artificial smoke test. 5 typical power is based on a voltage of v dd = 1.3 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 6 maximum power is based on a voltage of v dd = 1.3 v, worst case process, a junction temperature of t j = 105 c, and an artificial smoke test. table 4. mpc8347ea power dissipation 1 (continued) core frequency (mhz) csb frequency (mhz) typical at t j = 65 typical 2 , 3 maximum 4 unit
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 12 freescale semiconductor power characteristics table 5 shows the estimated typical i/o power dissipation for mpc8347ea. table 5. mpc8347ea typical i/o power dissipation interface parameter ddr2 gv dd (1.8 v) ddr1 gv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) unit comments ddr i/o 65% utilization 2.5 v rs = 20 rt = 50 2 pair of clocks 200 mhz, 32 bits 0.31 0.42 ? ? ? w ? 200 mhz, 64 bits 0.42 0.55 ? ? ? w ? 266 mhz, 32 bits 0.35 0.5 ? ? ? w ? 266 mhz, 64 bits 0.47 0.66 ? ? ? w ? 300 mhz, 1 32 bits 1 tbga package only. 0.37 0.54 ? ? ? w ? 300 mhz, 1 64 bits 0.50 0.7 ? ? ? w ? 333 mhz, 1 32 bits 0.39 0.58 ? ? ? w ? 333 mhz, 1 64 bits 0.53 0.76 ? ? ? w ? 400 mhz, 1 32 bits 0.44 ? ? ? ? ? 400 mhz, 1 64 bits 0.59 ? ? ? ? ? pci i/o load = 30 pf 33 mhz, 32 bits ? ? 0.04 ? ? w ? 66 mhz, 32 bits ? ? 0.07 ? ? w ? local bus i/o load = 25 pf 167 mhz, 32 bits ? ? 0.34 ? ? w ? 133 mhz, 32 bits ? ? 0.27 ? ? w ? 83 mhz, 32 bits ? ? 0.17 ? ? w ? 66 mhz, 32 bits ? ? 0.14 ? ? w ? 50 mhz, 32 bits ? ? 0.11 ? ? w ? tsec i/o load = 25 pf mii ? ? ? 0.01 ? w multiply by number of interfaces used. gmii or tbi ? ? ? 0.06 ? w rgmii or rtbi ? ? ? ? 0.04 w usb 12 mhz ? ? 0.01 ? ? w multiply by 2 if using 2 ports. 480 mhz ? ? 0.2 ? ? w other i/o ? ? 0.01 ? ? w ?
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 13 clock input timing 4 clock input timing this section provides the clock input dc and ac electrical characteristics for the device. 4.1 dc electrical characteristics table 6 provides the clock input (c lkin/pci_sync_in) dc timing sp ecifications for the mpc8347ea. 4.2 ac electrical characteristics the primary clock source for the mpc8347ea can be one of two input s, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. table 7 provides the clock input (clkin/pci_clk) ac timing sp ecifications for the device. table 6. clkin dc ti ming specifications parameter condition symbol min max unit input high voltage ? v ih 2.7 ov dd +0.3 v input low voltage ? v il ?0.3 0.4 v clkin input current 0 v v in ov dd i in ? 10 a pci_sync_in input current 0 v v in 0.5 v or ov dd ?0.5v v in ov dd i in ? 10 a pci_sync_in input current 0.5 v v in ov dd ? 0.5 v i in ? 50 a table 7. clkin ac timing specifications parameter/condition symbol min typical max unit notes clkin/pci_clk frequency f clkin ??66mhz1, 6 clkin/pci_clk cycle time t clkin 15 ? ? ns ? clkin/pci_clk rise and fall time t kh , t kl 0.6 1.0 2.3 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitte r ? ? ? 150 ps 4, 5 notes: 1. caution: the system, core, usb, security, and tsec must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for clkin/pci_clk are measured at 0.4 and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short te rm and long term?and is guaranteed by design. 5. the clkin/pci_clk driver?s closed loop jitter bandwidth should be < 500 khz at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter. 6. spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 khz modulation rate regardless of input frequency.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 14 freescale semiconductor reset initialization 4.3 tsec gigabit reference clock timing table 8 provides the tsec gigabit reference clocks (ec_gtx_clk125) ac timing specifications. 5 reset initialization this section describes the dc and ac electrical specifications for the reset initialization timing and electrical requirements of the mpc8347ea. 5.1 reset dc electrical characteristics table 9 provides the dc electrical characterist ics for the reset pins of the mpc8347ea. table 8. ec_gtx_clk125 ac timing specifications at recommended operating conditions with lv dd = 2.5 0.125 mv/ 3.3 v 165 mv parameter symbol min typical max unit notes ec_gtx_clk125 frequency t g125 ?125?mhz? ec_gtx_clk125 cycle time t g125 ?8?ns? ec_gtx_clk125 rise and fall time lv dd = 2.5 v lv dd = 3.3 v t g125r /t g125f ?? 0.75 1.0 ns 1 ec_gtx_clk125 duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %2 ec_gtx_clk125 jitter ? ? ? 150 ps 2 notes: 1. rise and fall times for ec_gtx_clk125 are measured from 0.5 and 2.0 v for lv dd = 2.5 v and from 0.6 and 2.7 v for lv dd =3.3v. 2. ec_gtx_clk125 is used to generate the gtx clock for the etsec transmitter with 2% degradation. the ec_gtx_clk125 duty cycle can be loosened from 47%/53% as long as the phy device can tolerate the duty cycle generated by the etsec gtx_clk. see section 8.2.4, ?rgmii and rtbi ac timing specifications for the duty cycle for 10base-t and 100base-t reference clock. table 9. reset pins dc electrical characteristics 1 parameter symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??5 a output high voltage 2 v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 15 reset initialization 5.2 reset ac electrical characteristics table 10 provides the reset initial ization ac timing specifi cations of the mpc8347ea. output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applie s for pins poreset , hreset , sreset , and quiesce . 2. hreset and sreset are open drain pins, thus v oh is not relevant for those pins. table 10. reset initializa tion timing specifications parameter min max unit notes required assertion time of hreset or sreset (input) to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to clkin when the mpc8347ea is in pci host mode 32 ? t clkin 2 required assertion time of poreset with stable clock applied to pci_sync_in when the mpc8347ea is in pci agent mode 32 ? t pci_sync_in 1 hreset /sreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to sreset negation (output) 16 ? t pci_sync_in 1 input setup time for por configurat ion signals (cfg_reset_source[0:2] and cfg_clkin_div) with respec t to negation of poreset when the mpc8347ea is in pci host mode 4?t clkin 2 input setup time for por configurat ion signals (cfg_reset_source[0:2] and cfg_clkin_div) with respec t to negation of poreset when the mpc8347ea is in pci agent mode 4?t pci_sync_in 1 input hold time for por configuration si gnals with respect to negation of hreset 0? ns? time for the mpc8347ea to turn off por configuration signals with respect to the assertion of hreset ?4 ns 3 time for the mpc8347ea to turn on por configuration signals with respect to the negation of hreset 1?t pci_sync_in 1, 3 notes: 1. t pci_sync_in is the clock period of the input clock applied to pci_sync_in. in pci host mode, the primary clock is applied to the clkin input, and pci_sync_in period depends on the value of cfg_clkin_div. see the mpc8349ea powerquicc ii pro integrated host processor family reference manual . 2. t clkin is the clock period of the input clock applied to clkin. it is valid only in pci host mode. see the mpc8349ea powerquicc ii pro integrated host processor family reference manual . 3. por configuration signals consist of cfg_reset_sou rce[0:2] and cfg_clkin_div. table 9. reset pins dc electrical characteristics 1 (continued) parameter symbol condition min max unit
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 16 freescale semiconductor ddr and ddr2 sdram table 11 lists the pll and dll lock times. 6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8347ea. note that ddr sdram is gv dd (typ) = 2.5 v and ddr2 sdram is gv dd (typ) = 1.8 v. the ac electrical specifications ar e the same for ddr and drr2 sdram. note the information in this document is accurate for revision 3.0 silicon and later. for information on revision 1.1 silicon and earlier versions see the mpc8347e powerquicc ii pro integrated host processor hardware specifications. see section 22.1, ?part numbers fully addressed by this document ,? for silicon revisi on level determination. 6.1 ddr and ddr2 sdram dc electrical characteristics table 12 provides the recommended ope rating conditions for the ddr2 sdram component(s) of the mpc8347ea when gv dd (typ) = 1.8 v . table 11. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s? dll lock times 7680 122,880 csb_clk cycles 1, 2 notes: 1. dll lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). a 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. the csb_clk is determined by th e clkin and system pll ratio. see section 19, ?clocking.? table 12. ddr2 sdram dc electr ical characteristics for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ?0.04 mv ref +0.04 v 3 input high voltage v ih mv ref + 0.125 gv dd +0.3 v ? input low voltage v il ?0.3 mv ref ?0.125 v ? output leakage current i oz ?9.9 9.9 a4 output high current (v out = 1.420 v) i oh ?13.4 ? ma ?
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 17 ddr and ddr2 sdram table 13 provides the ddr2 capacitance when gv dd (typ) = 1.8 v. table 14 provides the recommended ope rating conditions for the ddr sdram component(s) when gv dd (typ) = 2.5 v . output low current (v out = 0.280 v) i ol 13.4 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to equal 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref cannot exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to equal mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 13. ddr2 sdram capacitance for gv dd (typ) = 1.8 v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, dqs c io 68pf1 delta input/output capaci tance: dq, dqs, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 14. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ?0.04 mv ref +0.04 v 3 input high voltage v ih mv ref +0.18 gv dd +0.3 v ? input low voltage v il ?0.3 mv ref ?0.18 v ? output leakage current i oz ?9.9 ?9.9 a4 output high current (v out = 1.95 v) i oh ?15.2 ? ma ? output low current (v out = 0.35 v) i ol 15.2 ? ma ? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 12. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8 v (continued)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 18 freescale semiconductor ddr and ddr2 sdram table 15 provides the ddr capacitance when gv dd (typ) = 2.5 v. table 16 provides the current draw characteristics for mv ref . 6.2 ddr and ddr2 sdram ac electrical characteristics this section provides the ac el ectrical characteristics for th e ddr and ddr2 sdram interface. 6.2.1 ddr and ddr2 sdram input ac timing specifications table 17 provides the input ac timing specifications for the ddr2 sdram when gv dd (typ) = 1.8 v. table 18 provides the input ac timing specifications fo r the ddr sdram when gv dd (typ) = 2.5 v. table 15. ddr sdram capacitance for gv dd (typ) = 2.5 v parameter/condition symbol min max unit notes input/output capac itance: dq, dqs c io 68pf1 delta input/output ca pacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25c, v out = gv dd /2, v out (peak-to-peak) = 0.2 v. table 16. current draw characteristics for mv ref parameter/condition symbol min max unit note current draw for mv ref i mvref ?500 a1 note: 1. the voltage regulator for mv ref must supply up to 500 a current. table 17. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions with gv dd of 1.8 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.25 v ? ac input high voltage v ih mv ref + 0.25 ? v ? table 18. ddr sdram input ac timing specifications for 2.5-v interface at recommended operating conditions with gv dd of 2.5 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ? ac input high voltage v ih mv ref + 0.31 ? v ?
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 19 ddr and ddr2 sdram table 19 provides the input ac ti ming specifications for the ddr sdram interface. figure 5 illustrates the ddr input timing diagram showing the t diskew timing parameter. figure 5. ddr input timing diagram table 19. ddr and ddr2 sdram in put ac timing specifications at recommended operating conditions with gv dd of (1.8 or 2.5 v) 5%. parameter symbol min max unit notes controller skew for mdqs?mdq/mecc/mdm t ciskew ps 1, 2 400 mhz ?600 600 3 333 mhz ?750 750 ? 266 mhz ?750 750 ? 200 mhz ?750 750 ? notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the equation: t diskew = (t/4 ? abs (t ciskew )); where t is the clock period and abs (t ciskew ) is the absolute value of t ciskew . 3. this specification applies only to the ddr interface. mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 20 freescale semiconductor ddr and ddr2 sdram 6.2.2 ddr and ddr2 sdram outp ut ac timing specifications table 20 shows the ddr and ddr2 output ac timing specifications. table 20. ddr and ddr2 sdram ou tput ac timing specifications at recommended operating conditions with gv dd of (1.8 or 2.5 v) 5%. parameter symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) (pbga package) t mck 5?ns2 mck[n] cycle time, (mck[n]/mck [n] crossing) (tbga package) t mck 7.5 ? ns 2 addr/cmd/modt output set up with respect to mck t ddkhas ns 3 400 mhz 1.95 ? 333 mhz 2.40 ? 266 mhz 3.15 ? 200 mhz 4.20 ? addr/cmd/modt ou tput hold with respect to mck t ddkhax ns 3 400 mhz 1.95 ? 333 mhz 2.40 ? 266 mhz 3.15 ? 200 mhz 4.20 ? mcs (n) output setup with respect to mck t ddkhcs ns 3 400 mhz 1.95 ? 333 mhz 2.40 ? 266 mhz 3.15 ? 200 mhz 4.20 ? mcs (n) output hold with respect to mck t ddkhcx ns 3 400 mhz 1.95 ? 333 mhz 2.40 ? 266 mhz 3.15 ? 200 mhz 4.20 ? mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mdq/mecc/mdm output se tup with respect to mdqs t ddkhds, t ddklds ps 5 400 mhz 700 ? 333 mhz 775 ? 266 mhz 1100 ? 200 mhz 1200 ? mdq/mecc/mdm output hold with respect to mdqs t ddkhdx, t ddkldx ps 5 400 mhz 700 ? 333 mhz 900 ?
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 21 ddr and ddr2 sdram figure 6 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 6. timing diagram for t ddkhmh 266 mhz 1100 ? 200 mhz 1200 ? mdqs preamble start t ddkhmp ?0.5 t mck ? 0.6 ?0.5 t mck + 0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output goes invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are set up (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 4. t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 regi ster and is typically set to the same del ay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these two param eters are set to the same adjustment value. see the mpc8349ea powerquicc ii pro integrated host processor family reference manual for the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck( n) at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. table 20. ddr and ddr2 sdram output ac timing specifi cations (continued) at recommended operating conditions with gv dd of (1.8 or 2.5 v) 5%. parameter symbol 1 min max unit notes mdqs mck [n] mck[n] t mck mdqs t ddkhmh(min) = ?0.6 ns t ddkhmhmax) = 0.6 ns
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 22 freescale semiconductor duart figure 7 shows the ddr sdram output timing diagram. figure 7. ddr sdram output timing diagram figure 8 provides the ac test load for the ddr bus. figure 8. ddr ac test load 7duart this section describes the dc and ac electrical specifications for the duart interface of the mpc8347ea. 7.1 duart dc electrical characteristics table 21 provides the dc electrical characteristics for the duart interface of the mpc8347ea. table 21. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (0.8 v v in 2 v) i in ?5 a addr/cmd/modt t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhmp t ddkhas ,t ddkhcs t ddkhme output z 0 = 50 r l = 50 gv dd /2
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 23 ethernet: three-speed ethernet, mii management 7.2 duart ac electrical specifications table 22 provides the ac timing parameters fo r the duart interface of the mpc8347ea. 8 ethernet: three-speed ethernet, mii management this section provides the ac and dc electrical char acteristics for three-spee ds (10/100/1000 mbps) and mii management. 8.1 three-speed ethernet controller (tsec)?gmii/mii/tbi/ rgmii/rtbi electri cal characteristics the electrical characteristics speci fied here apply to gigabit media independent interface (gmii), the media independent interface (mii), ten-bit inte rface (tbi), reduced gigabit media independent interface (rgmii), and reduced ten-bit interface (r tbi) signals except manage ment data input/output (mdio) and management data clock (mdc). the mii, gmii, and tbi interfaces are defined for 3.3 v, and the rgmii and rtbi interfaces are defined for 2.5 v. the rgmii and rtbi interfaces follow the hewlett-packard reduced pin-count interface for gigabit ethernet physical layer device specification , version 1.2a (9/22/2000). the electrical characte ristics for mdio and mdc are specified in section 8.3, ?ethernet management interf ace electrical characteristics.? high-level output voltage, i oh = ?100 av oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v table 22. duart ac timing specifications parameter value unit notes minimum baud rate 256 baud ? maximum baud rate > 1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate will be limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. table 21. duart dc electrical characteristics (continued) parameter symbol min max unit
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 24 freescale semiconductor ethernet: three-speed ethernet, mii management 8.1.1 tsec dc electrical characteristics gmii, mii, tbi, rgmii, and rtbi drivers and recei vers comply with the dc parametric attributes specified in table 23 and table 24 . the rgmii and rtbi signals in table 24 are based on a 2.5-v cmos interface voltage as defi ned by jedec eia/jesd8-5. 8.2 gmii, mii, tbi, rgmii, an d rtbi ac timing specifications the ac timing specifications for gm ii, mii, tbi, rgmii, and rtbi are presented in this section. 8.2.1 gmii timing specifications this section describes the gmii transm it and receive ac timing specifications. table 23. gmii/tbi and mii dc electrical characteristics parameter symbol conditions min max unit supply voltage 3.3 v lv dd 2 ? 2.97 3.63 v output high voltage v oh i oh = ?4.0 ma lv dd = min 2.40 lv dd +0.3 v output low voltage v ol i ol = 4.0 ma lv dd = min gnd 0.50 v input high voltage v ih ??2.0lv dd +0.3 v input low voltage v il ? ? ?0.3 0.90 v input high current i ih v in 1 = lv dd ?40 a input low current i il v in 1 = gnd ?600 ? a notes: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . 2. gmii/mii pins not needed for rgmii or rtbi operation are powered by the ov dd supply. table 24. rgmii/rtbi (when operating at 2.5 v) dc electrical characteristics parameters symbol conditions min max unit supply voltage 2.5 v lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd +0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd ? 0.3 0.40 v input high voltage v ih ?lv dd = min 1.7 lv dd +0.3 v input low voltage v il ?lv dd = min ?0.3 0.70 v input high current i ih v in 1 = lv dd ?10 a input low current i il v in 1 = gnd ?15 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 .
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 25 ethernet: three-speed ethernet, mii management 8.2.1.1 gmii transmit ac timing specifications table 25 provides the gmii transmit ac timing specifications. figure 9 shows the gmii transm it ac timing diagram. figure 9. gmii transmit ac timing diagram 8.2.1.2 gmii receive ac timing specifications table 26 provides the gmii receiv e ac timing specifications. table 25. gmii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t gtx ?8.0 ? ns gtx_clk duty cycle t gtxh /t gtx 43.75 ? 56.25 % gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk clock rise time (20%?80%) t gtxr ??1.0ns gtx_clk clock fall time (80%?20%) t gtxf ??1.0ns notes: 1. the symbols for timing specif ications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relati ve to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. in genera l, the clock reference symbol is based on three letters representing the clock of a particular function. for example, the subscrip t of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 26. gmii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0?ns rx_clk duty cycle t grxh /t grx 40 ? 60 % rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf tx_en tx_er
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 26 freescale semiconductor ethernet: three-speed ethernet, mii management figure 10 shows the gmii receive ac timing diagram. g figure 10. gmii receive ac timing diagram 8.2.2 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 8.2.2.1 mii transmit ac timing specifications table 27 provides the mii transmit ac timing specifications. rx_clk clock rise (20%?80%) t grxr ??1.0ns rx_clk clock fall time (80%?20%) t grxf ??1.0ns note: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d ) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. in general, the clock reference symbol is based on three letters representing the clock of a particular func tion. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall ti mes, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 27. mii transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns table 26. gmii receive ac timing specifications (continued) at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 27 ethernet: three-speed ethernet, mii management figure 11 shows the mii transm it ac timing diagram. figure 11. mii transmit ac timing diagram 8.2.2.2 mii receive ac timing specifications table 28 provides the mii receive ac timing specifications. tx_clk data clock rise (20%?80%) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall (80%?20%) t mtxf 1.0 ? 4.0 ns note: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). in general, the clock reference symbol is based on two to three letters representing the clock of a particular function. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convent ion is used with the appropriate letter: r (rise) or f (fall). table 28. mii receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx ? 400 ? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns table 27. mii transmit ac timing specifications (continued) at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 28 freescale semiconductor ethernet: three-speed ethernet, mii management figure 12 provides the ac test load for tsec. figure 12. tsec ac test load figure 13 shows the mii receive ac timing diagram. figure 13. mii receive ac timing diagram 8.2.3 tbi ac timing specifications this section describes the tbi transmit and receive ac ti ming specifications. rx_clk clock rise (20%?80%) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time (80%?20%) t mrxf 1.0 ? 4.0 ns note: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. in general, the clock reference symbol is based on three letters representing the cl ock of a particular function. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall time s, the latter convention is us ed with the appropriate letter: r (rise) or f (fall). table 28. mii receive ac timing specifications (continued) at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit output z 0 = 50 ov dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 29 ethernet: three-speed ethernet, mii management 8.2.3.1 tbi transmit ac timing specifications table 29 provides the tbi transmit ac timing specifications. figure 14 shows the tbi transmit ac timing diagram. figure 14. tbi transmit ac timing diagram 8.2.3.2 tbi receive ac timing specifications table 30 provides the tbi receive ac timi ng specifications. table 29. tbi transmit ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t ttx ?8.0?ns gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % gtx_clk to tbi data txd[7:0], tx_er, tx_en delay t ttkhdx 1.0 ? 5.0 ns gtx_clk clock rise (20%?80%) t ttxr ??1.0ns gtx_clk clock fall time (80%?20%) t ttxf ??1.0ns notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (t t) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. in general, the clock reference symbol is based on three letters representing the clock of a particular function. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 30. tbi receive ac timing specifications at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit pma_rx_clk clock period t trx 16.0 ns pma_rx_clk skew t sktrx 7.5 ? 8.5 ns rx_clk duty cycle t trxh /t trx 40 ? 60 % gtx_clk txd[7:0] t ttx t ttxh t ttxr t ttxf t ttkhdx tx_en tx_er
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 30 freescale semiconductor ethernet: three-speed ethernet, mii management figure 15 shows the tbi receive ac timing diagram. figure 15. tbi receive ac timing diagram rxd[7:0], rx_dv, rx_er (rcg[9:0]) setup time to rising pma_rx_clk t trdvkh 2 2.5 ? ? ns rxd[7:0], rx_dv, rx_er (rcg[9:0]) hold time to rising pma_rx_clk t trdxkh 2 1.5 ? ? ns rx_clk clock rise time (20%?80%) t trxr 0.7 ? 2.4 ns rx_clk clock fall time (80%?20%) t trxf 0.7 ? 2.4 ns notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. in general, the clock reference symbol is based on three letters representing the clock of a particular function. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter conv ention is used with the appropriate letter: r (rise) or f (fall ). for symbols representing skews, the subscript sk follow ed by the clock that is being skewed (trx). 2. setup and hold time of even numbered rcg are measured fr om the riding edge of pma_rx_clk1. setup and hold times of odd-numbered rcg are measured from the riding edge of pma_rx_clk0. table 30. tbi receive ac timing specifications (continued) at recommended operating conditions with lv dd /ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t trxh even rcg odd rcg t sktrx
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 31 ethernet: three-speed ethernet, mii management 8.2.4 rgmii and rtbi ac timing specifications table 31 presents the rgmii and rt bi ac timing specifications. table 31. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt ?0.5 ? 0.5 ns data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock cycle duration 3 t rgt 7.2 8.0 8.8 ns duty cycle for 1000base-t 4, 5 t rgth /t rgt 45 50 55 % duty cycle for 10base-t and 100base-tx 3, 5 t rgth /t rgt 40 50 60 % rise time (20%?80%) t rgtr ? ? 0.75 ns fall time (80%?20%) t rgtf ? ? 0.75 ns notes: 1. in general, the clock reference symbol for this section is based on the symbols rgt to repres ent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. also, the notation for rise (r) and fall (f) times follows the clock symbol. for symbols representing skews, t he subscript is sk followed by the clock being skewed (rgt). 2. this implies that pc board design requires clocks to be rout ed so that an additional trace de lay of greater than 1.5 ns is add ed to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long as the minimum duty cycle is not violated and st retching occurs for no more than three t rgt of the lowest speed transitioned. 5. duty cycle reference is lv dd /2.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 32 freescale semiconductor ethernet: three-speed ethernet, mii management figure 16 shows the rbmii and rtbi ac timing and multiplexing diagrams. figure 16. rgmii and rtbi ac timing and multiplexing diagrams 8.3 ethernet management interface electrical characteristics the electrical characteristics speci fied here apply to the mii manage ment interface signals management data input/output (mdio) and manage ment data clock (mdc). the elec trical characteristics for gmii, rgmii, tbi and rtbi are specified in section 8.1, ?three-speed ethernet controller (tsec)?gmii/mii/tbi/rgmii/rt bi electrical characteristics .? 8.3.1 mii management dc electrical characteristics the mdc and mdio are defi ned to operate at a supply voltage of 2.5 or 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 32 and table 33 . table 32. mii management dc electrical characteristics powered at 2.5 v parameter symbol conditions min max unit supply voltage (2.5 v) lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd +0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd ? 0.3 0.40 v input high voltage v ih ?lv dd = min 1.7 ? v input low voltage v il ?lv dd = min ?0.3 0.70 v gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 33 ethernet: three-speed ethernet, mii management 8.3.2 mii management ac electrical specifications table 34 provides the mii management ac timing specifications. input high current i ih v in 1 = lv dd ?10 a input low current i il v in = lv dd ?15 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . table 33. mii management dc electrical characteristics powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) lv dd ? 2.97 3.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.10 lv dd +0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd 0.50 v input high voltage v ih ?2.00?v input low voltage v il ? ? 0.80 v input high current i ih lv dd = max v in 1 = 2.1 v ? 40 a input low current i il lv dd = max v in = 0.5 v ?600 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . table 34. mii management ac timing specifications at recommended operating conditions with lv dd is 3.3 v 10% or 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc ?2.5?mhz2 mdc period t mdc ?400?ns? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio delay t mdkhdx 10 ? 70 ns 3 mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns ? table 32. mii management dc electrical characteristics powered at 2.5 v (continued) parameter symbol conditions min max unit
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 34 freescale semiconductor ethernet: three-speed ethernet, mii management figure 17 shows the mii management ac timing diagram. figure 17. mii management interface timing diagram mdc fall time t mdhf ? ? 10 ns ? notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a csb_clk of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz). 3. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 mhz, the delay is 70 ns and for a csb_clk of 333 mhz, the delay is 58 ns). table 34. mii management ac timing specifications (continued) at recommended operating conditions with lv dd is 3.3 v 10% or 2.5 v 5%. parameter/condition symbol 1 min typ max unit notes mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 35 usb 9usb this section provides the ac and dc electrical sp ecifications for the usb interface of the mpc8347ea. 9.1 usb dc electrical characteristics table 35 provides the dc electrical characteristics for the usb interface. 9.2 usb ac electrical specifications table 36 describes the general timing parameters of the usb interface of the mpc8347ea. table 35. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd +0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?5 a high-level output voltage, i oh = ?100 av oh ov dd ?0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v table 36. usb general timing parameters (ulpi mode only) parameter symbol 1 min max unit notes usb clock cycle time t usck 15 ? ns 2?5 input setup to usb clock?all inputs t usivkh 4 ? ns 2?5 input hold to usb clock?all inputs t usixkh 1 ? ns 2?5 usb clock to output valid?all outputs t uskhov ? 7 ns 2?5 output hold from usb clock?all outputs t uskhox 2 ? ns 2?5 notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t usixkh symbolizes usb timing (us) for the input (i) to go invalid (x) with respect to the time the usb clock reference (k) goes high (h). also, t uskhox symbolizes usb timing (us) for the usb clock reference (k) to go high (h), with respect to the output (o) goi ng invalid (x) or output hold time. 2. all timings are in reference to usb clock. 3. all signals are measured from ov dd /2 of the rising edge of the usb clock to 0.4 ov dd of the signal in question for 3.3 v signaling levels. 4. input timings are measured at the pin. 5. for active/float timing measurements, the hi-z or off-stat e is defined to be when the total current delivered through the component pin is less than or equal to th at of the leakage current specification.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 36 freescale semiconductor local bus figure 18 and figure 19 provide the ac test load and signals for the usb, respectively. figure 18. usb ac test load figure 19. usb signals 10 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8347ea. 10.1 local bus dc electrical characteristics table 37 provides the dc electrical characteristics for the local bus interface. table 37. local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd +0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?5 a high-level output voltage, i oh = ?100 av oh ov dd ?0.2 ? v low-level output voltage, i ol = 100 av ol ?0.2v output z 0 = 50 ov dd /2 r l = 50
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 37 local bus 10.2 local bus ac electrical specification table 38 and table 39 describe the general ti ming parameters of the local bus interface of the mpc8347ea. table 38. local bus general timing parameters?dll on parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 ? ns 2 input setup to local bus clock (except lupwait) t lbivkh1 1.5 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 2.2 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to lale rise t lbkhlr ?4.5ns? local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?4.5ns? local bus clock to data valid for lad/ldp t lbkhov2 ?4.5ns3 local bus clock to address valid for lad t lbkhov3 ?4.5ns3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 1?ns3 output hold from local bus clock for lad/ldp t lbkhox2 1?ns3 local bus clock to output high impedance for lad/ldp t lbkhoz ?3.8ns8 notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x ) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to the rising edge of lsync_in. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in to 0.4 ov dd of the signal in question for 3.3 v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and when the load on the lale output pin is at least 10 pf less than the load on the lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and when the load on the lale output pin is at least 10 pf less than the load on the lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and when the load on the lale output pin equals the load on the lad output pins. 8. for active/float timing measurements, the hi-z or off-stat e is defined to be when the total current delivered through the component pin is less than or equal to th at of the leakage current specification.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 38 freescale semiconductor local bus figure 20 provides the ac test load for the local bus. figure 20. local bus c test load table 39. local bus general timing parameters?dll bypass 9 parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to lo cal bus clock t lbivkh 7 ? ns 3, 4 input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to output valid t lbklov ?3ns3 local bus clock to output high impedance for lad/ldp t lbkhoz ?4ns8 notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x ) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one (1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to the falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or the rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3 v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is set and when the load on the lale output pin is at least 10 pf less than the load on the lad output pins. 6. t lbotot2 should be used when rcwh[lale] is not set and when the load on the lale output pin is at least 10 pf less than the load on the lad output pins.the 7. t lbotot3 should be used when rcwh[lale] is not set and when th e load on the lale output pin equals to the load on the lad output pins. 8. for purposes of active/float timing meas urements, the hi-z or off-state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 9. dll bypass mode is not recommended for use at frequencies above 66 mhz. output z 0 = 50 ov dd /2 r l = 50
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 39 local bus figure 21 through figure 26 show the local bus signals. figure 21. local bus signals, nons pecial signals only (dll enabled) figure 22. local bus signals, nonspecial signals only (dll bypass mode) output signals: la[27:31]/lbctl/lbcke/loe lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov t lbkhov lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh t lbivkh t lbixkh t lbkhox t lbkhoz t lbkhlr t lbotot t lbkhoz t lbkhox output signals: lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] lclk[n] input signals: lad[0:31]/ldp[0:3] output signals: lad[0:31]/ldp[0:3] lale input signal: lgta t lbixkh t lbklov t lbkhoz t lbotot t lbivkh t lbixkh t lbklov t lbklov t lbivkh la[27:31]/lbctl/lbcke/loe
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 40 freescale semiconductor local bus figure 23. local bus signals, gpcm/upm si gnals for lccr[clkdiv] = 2 (dll enabled) figure 24. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (dll bypass mode) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov t lbklov t lbkhoz (dll bypass mode)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 41 local bus figure 25. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (dll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov t lbklov t lbkhoz t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 42 freescale semiconductor jtag figure 26. local bus signals, gpcm/upm si gnals for lccr[clkdiv] = 4 (dll enabled) 11 jtag this section describes the dc and ac electrical specificat ions for the ieee std. 1149.1 (jtag) interface of the mpc8347ea. 11.1 jtag dc electrical characteristics table 40 provides the dc electrical ch aracteristics for the ieee std. 1149.1 (jtag) interface of the mpc8347ea. table 40. jtag interface dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ?ov dd ?0.3 ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 43 jtag 11.2 jtag ac timing specifications this section describes the ac el ectrical specifications for the ieee std. 1149.1 (jtag) interface of the mpc8347ea. table 41 provides the jtag ac timing sp ecifications as defined in figure 28 through figure 31 . output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 41. jtag ac timing specifications (independent of clkin) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr , t jtgf 02ns? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 table 40. jtag interface dc electrical characteristics (continued) parameter symbol condition min max unit
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 44 freescale semiconductor jtag figure 27 provides the ac test load for tdo a nd the boundary-scan outputs of the mpc8347ea. figure 27. ac test load for the jtag interface figure 28 provides the jtag clock input timing diagram. figure 28. jtag clock input timing diagram figure 29 provides the trst timing diagram. figure 29. trst timing diagram jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50 load (see figure 18 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols for timing specifications follow the pattern of t (first two letters of functional bl ock)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d ) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. in general, the clock reference symbol is based on three letters representing the clock of a particular functi on. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization. table 41. jtag ac timing specific ations (independent of clkin) 1 (continued) at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 45 jtag figure 30 provides the boundary-scan timing diagram. figure 30. boundary-scan timing diagram figure 31 provides the test access port timing diagram. figure 31. test access port timing diagram vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 46 freescale semiconductor i 2 c 12 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8347ea. 12.1 i 2 c dc electrical characteristics table 42 provides the dc electrical characteristics for the i 2 c interface of the mpc8347ea. 12.2 i 2 c ac electrical specifications table 43 provides the ac timing parameters for the i 2 c interface of the mpc8347ea. note that all values refer to v ih (min) and v il (max) levels (see table 42 ). table 42. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 10%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.2 ov dd v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a4 capacitance for each i/o pin c i ?10pf? notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8349ea integrated host processor family reference manual, for information on the digital filter used. 4. i/o pins obstruct the sda and scl lines if ov dd is switched off. table 43. i 2 c ac electrical specifications parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns data hold time:cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 47 i 2 c figure 32 provides the ac test load for the i 2 c. figure 32. i 2 c ac test load figure 33 shows the ac timing diagram for the i 2 c bus. figure 33. i 2 c bus ac timing diagram fall time of both sda and scl signals 5 t i2cf __ 300 ns setup time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the dat a with respect to the start condition (s) goes invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaches the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp riate letter: r (rise) or f (fall). 2. the device provides a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh must be met only if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. 5.)the device does not follow the ?i 2 c-bus specifications? version 2.1 regarding the t i2cf ac parameter. table 43. i 2 c ac electrical specifications (continued) parameter symbol 1 min max unit output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 48 freescale semiconductor pci 13 pci this section describes the dc and ac electrical specifications for the pci bus of the mpc8347ea. 13.1 pci dc electrical characteristics table 44 provides the dc electrical characteristic s for the pci interface of the mpc8347ea. 13.2 pci ac electrical specifications this section describes the general ac timing parameters of the pci bus of the mpc8347ea. note that the pci_clk or pci_sync_in signal is used as the pc i input clock depending on whether the device is configured as a host or agent device. table 45 provides the pci ac timing specifications at 66 mhz. table 44. pci dc electrical characteristics parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd +0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v input current i in v in 1 = 0 v or v in = ov dd ?5 a high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ?0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a ?0.2v note: 1. the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 . table 45. pci ac timing specifications at 66 mhz 1 parameter symbol 2 min max unit notes clock to output valid t pckhov ?6.0ns3 output hold from clock t pckhox 1?ns3 clock to output high impedance t pckhoz ?14ns3, 4 input setup to clock t pcivkh 3.0 ? ns 3, 5
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 49 pci table 46 provides the pci ac timing specifications at 33 mhz. figure 34 provides the ac test load for pci. figure 34. pci ac test load input hold from clock t pcixkh 0 ? ns 3, 5 notes: 1. pci timing depends on m66en and the ratio between pci1/pci2. refer to the pci chapter of the reference manual for a description of m66en. 2. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the va lid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 3. see the timing measurement conditions in the pci 2.3 local bus specifications . 4. for active/float timing measurements, the hi-z or off-stat e is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. table 46. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 notes: 1. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the va lid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for active/float timing measurements, the hi-z or off-stat e is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. table 45. pci ac timing specifications at 66 mhz 1 (continued) parameter symbol 2 min max unit notes output z 0 = 50 ov dd /2 r l = 50
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 50 freescale semiconductor timers figure 35 shows the pci input ac timing diagram. figure 35. pci input ac timing diagram figure 36 shows the pci output ac timing diagram. figure 36. pci output ac timing diagram 14 timers this section describes the dc and ac electrical specifications for the timers. 14.1 timer dc electrical characteristics table 47 provides the dc electrical characteristics fo r the mpc8347ea timer pi ns, including tin, tout , tgate , and rtc_clk. table 47. timer dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 51 gpio 14.2 timer ac timing specifications table 48 provides the timer input and output ac timing specifications. 15 gpio this section describes the dc and ac electrical specifications for the gpio. 15.1 gpio dc electrical characteristics table 49 provides the dc electrical charac teristics for the mpc8347ea gpio. 15.2 gpio ac timing specifications table 50 provides the gpio i nput and output ac ti ming specifications. table 48. timers input ac timing specifications 1 parameter symbol 2 min unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measur ed from the 50 percent level of the signal to th e 50 percent level of the rising edge of clkin . timings are measured at the pin. 2. timer inputs and outputs are asynchronous to any visible cloc k. timer outputs should be synchronized before use by external synchronous logic. timer inputs are required to be valid for at least t tiwid ns to ensure proper operation. table 49. gpio dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v input current i in ??5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 50. gpio input ac timing specifications 1 parameter symbol 2 min unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measur ed from the 50 percent level of the signal to th e 50 percent level of the rising edge of clkin . timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to any visible cloc k. gpio outputs should be synchronized before use by external synchronous logic. gpio inputs mu st be valid for at least t piwid ns to ensure proper operation.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 52 freescale semiconductor ipic 16 ipic this section describes the dc and ac electrical specifications for the external interrupt pins. 16.1 ipic dc electrical characteristics table 51 provides the dc electrical characteris tics for the external interrupt pins. 16.2 ipic ac timing specifications table 52 provides the ipic input and output ac timing specifications. 17 spi this section describes the spi dc and ac electrical specifications. 17.1 spi dc electrical characteristics table 53 provides the spi dc el ectrical characteristics. table 51. ipic dc electrical characteristics 1 parameter symbol condi tion min max unit notes input high voltage v ih ?2.0ov dd +0.3 v ? input low voltage v il ??0.30.8v? input current i in ??5 a? output low voltage v ol i ol = 8.0 ma ? 0.5 v 2 output low voltage v ol i ol = 3.2 ma ? 0.4 v 2 notes: 1. this table applies for pins irq [0:7], irq_out , and mcp_out . 2. irq_out and mcp_out are open-drain pins; thus v oh is not relevant for those pins. table 52. ipic input ac timing specifications 1 parameter symbol 2 min unit ipic inputs?minimum pulse width t picwid 20 ns notes: 1. input specifications are meas ured at the 50 percent level of the ipic input signals. timings are measured at the pin. 2. ipic inputs and outputs are asynchronous to any visible cloc k. ipic outputs should be synchronized before use by external synchronous logic. ipic inputs must be valid for at least t picwid ns to ensure proper operation in edge triggered mode. table 53. spi dc electrical characteristics parameter symbol condition min max unit input high voltage v ih ?2.0ov dd +0.3 v input low voltage v il ??0.30.8v
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 53 spi 17.2 spi ac timing specifications table 54 provides the spi input and out put ac timing specifications. figure 37 provides the ac test load for the spi. figure 37. spi ac test load input current i in ??5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 54. spi ac timing specifications 1 parameter symbol 2 min max unit spi outputs valid?master mode (internal clock) delay t nikhov ?6ns spi outputs hold?master mode (internal clock) delay t nikhox 0.5 ? ns spi outputs valid?slave mode (external clock) delay t nekhov ?8ns spi outputs hold?slave mode (external clock) delay t nekhox 2?ns spi inputs?master mode (internal clock input setup time t niivkh 4?ns spi inputs?master mode (internal clock input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns notes: 1. output specifications are measured from the 50 percent level of the rising edge of cl kin to the 50 percent level of the signa l. timings are measured at the pin. 2. the symbols for timing specific ations follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spiclk clock refere nce (k) goes to the high state (h ) until outputs (o) are invalid (x). table 53. spi dc electrical characteristics (continued) parameter symbol condition min max unit output z 0 = 50 ov dd /2 r l = 50
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 54 freescale semiconductor package and pin listings figure 38 and figure 39 represent the ac timings from table 54 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. figure 38 shows the spi timings in sl ave mode (external clock). figure 38. spi ac timing in slave mode (external clock) diagram figure 39 shows the spi timings in ma ster mode (internal clock). figure 39. spi ac timing in master mode (internal clock) diagram 18 package and pin listings this section details package para meters, pin assignments, and dimens ions. the mpc8347ea is available in two packages?a tape ball grid array (tb ga) and a plastic ball grid array (pbga). see section 18.1, ?package parameters for the mpc8347ea tbga,? section 18.2, ?mechanical dimensions for the mpc8347ea tbga,? section 18.3, ?package pa rameters for the mpc8347ea pbga,? and section 18.4, ?mechanical dimens ions for the mpc8347ea pbga.? 18.1 package parameters for the mpc8347ea tbga the package parameters are provided in the following list. the package type is 35 mm 35 mm, 672 tape ball grid array (tbga). package outline 35 mm 35 mm interconnects 672 spiclk (input) t neixkh t neivkh t nekhox input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhox input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 55 package and pin listings pitch 1.00 mm module height (typical) 1.46 mm solder balls 62 sn/36 pb/2 ag (zu package) 96.5 sn/3.5ag (vv package) ball diameter (typical) 0.64 mm
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 56 freescale semiconductor package and pin listings 18.2 mechanical dimensions for the mpc8347ea tbga figure 40 shows the mechanical dimensions and bottom surface nomenclature for the mpc8347ea, 672-tbga package. figure 40. mechanical dimensions and bottom surface nomenclature for the mpc8347ea tbga notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement must exclude any ef fect of mark on top surface of package.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 57 package and pin listings 18.3 package parameters for the mpc8347ea pbga the package parameters are as provided in th e following list. the package type is 29 mm 29 mm, 620 plastic ball grid array (pbga). package outline 29 mm 29 mm interconnects 620 pitch 1.00 mm module height (maximum) 2.46 mm module height (typical) 2.23 mm module height (minimum) 2.00 mm solder balls 62 sn/36 pb/2 ag (zq package) 96.5 sn/3.5ag (vr package) ball diameter (typical) 0.60 mm
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 58 freescale semiconductor package and pin listings 18.4 mechanical dimensions for the mpc8347ea pbga figure 41 shows the mechanical dimensions and bottom surface nomenclatur e for the mpc8347ea, 620-pbga package. notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14. 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. figure 41. mechanical dimensions and bottom surface nomenclature for the mpc8347ea pbga
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 59 package and pin listings 18.5 pinout listings table 55 provides the pinout lis ting for the mpc8347ea, 672 tbga package. table 55. mpc8347ea (t bga) pinout listing signal package pin number pin type power supply notes pci pci_inta /irq_out b34 o ov dd 2 pci_reset_out c33 o ov dd ? pci_ad[31:0] g30, g32, g34, h31, h32, h33, h34, j29, j32, j33, l30, k31, k33, k34, l33, l34, p34, r29, r30, r33, r34, t31, t32, t33, u31, u34, v31, v32, v33, v34, w33, w34 i/o ov dd ? pci_c/be [3:0] j30, m31, p33, t34 i/o ov dd ? pci_par p32 i/o ov dd ? pci_frame m32 i/o ov dd 5 pci_trdy n29 i/o ov dd 5 pci_irdy m34 i/o ov dd 5 pci_stop n31 i/o ov dd 5 pci_devsel n30 i/o ov dd 5 pci_idsel j31 i ov dd ? pci_serr n34 i/o ov dd 5 pci_perr n33 i/o ov dd 5 pci_req [0] d32 i/o ov dd ? pci_req [1]/cpci1_hs_es d34 i ov dd ? pci_req [2:4] e34, f32, g29 i ov dd ? pci_gnt0 c34 i/o ov dd ? pci_gnt1 /cpci1_hs_led d33 o ov dd ? pci_gnt2 / cpci1_hs_enum e33 o ov dd ? pci _gnt [3:4] f31, f33 o ov dd ? m66en a19 i ov dd ? ddr sdram memory interface mdq[0:63] d5, a3, c3, d3 , c4, b3, c2, d4, d2, e5, g2, h6, e4, f3, g4, g3, h1, j2, l6, m6, h2, k6, l2, m4, n2, p4, r2, t4, p6, p3, r1, t2, ab5, aa3, ad6, ae4, ab4, ac2, ad3, ae6, ae3, ag4, ak5, ak4, ae2, ag6, ak3, ak2, al2, al1, am5, ap5, am2, an1, ap4, an5, aj7, an7, am8, aj9, ap6, al7, al9, an8 i/o gv dd ?
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 60 freescale semiconductor package and pin listings mecc[0:4]/msrcid[0:4] w4, w3, y3, aa6, t1 i/o gv dd ? mecc[5]/mdval u1 i/o gv dd ? mecc[6:7] y1, y6 i/o gv dd ? mdm[0:8] b1, f1, k1, r4, ad4, aj1, ap3, ap7, y4 ogv dd ? mdqs[0:8] b2, f5, j1, p2, ac1, aj2, an4, al8, w2 i/o gv dd ? mba[0:1] ad1, aa5 o gv dd ? ma[0:14] w1, u4, t3, r3, p1, m1, n1, l3, l1, k2, y2, k3, j3, ap2, an6 ogv dd ? mwe af1 o gv dd ? mras af4 o gv dd ? mcas ag3 o gv dd ? mcs [0:3] ag2, ag1, ak1, al4 o gv dd ? mcke[0:1] h3, g1 o gv dd 3 mck[0:5] u2, f4, am3, v3, f2, an3 o gv dd ? mck [0:5] u3, e3, an2, v4, e1, am4 o gv dd ? modt[0:3] ah3, aj5, ah1, aj4 o gv dd ? mba[2] h4 o gv dd ? mdic0 ab1 i/o ? 10 mdic1 aa1 i/o ? 10 local bus controller interface lad[0:31] am13, ap13, al14, am14, an14, ap14, ak15, aj15, am15, an15, ap15, am16, al16, an16, ap16, al17, am17, ap17, ak17, ap18, al18, am18, an18, ap19, an19, am19, ap20, ak19, an20, al20, ap21, an21 i/o ov dd ? ldp[0]/ckstop_out am21 i/o ov dd ? ldp[1]/ckstop_in ap22 i/o ov dd ? ldp[2]/lcs [4] an22 i/o ov dd ? ldp[3]/lcs [5] am22 i/o ov dd ? la[27:31] ak21, ap23, an23, ap24, ak22 o ov dd ? lcs [0:3] an24, al23, ap25, an25 o ov dd ? lwe [0:3]/lsddqm[0:3]/lbs [0:3] ak23, ap26, al24, am25 o ov dd ? lbctl an26 o ov dd ? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 61 package and pin listings lale ak24 o ov dd ? lgpl0/lsda10/cfg_reset_source0 ap27 i/o ov dd ? lgpl1/lsdwe /cfg_reset_source1 al25 i/o ov dd ? lgpl2/lsdras /loe aj24 o ov dd ? lgpl3/lsdcas/ cfg_reset_source2 an27 i/o ov dd ? lgpl4/lgta /lupwait/lpbse ap28 i/o ov dd 13 lgpl5/cfg_clkin_div al26 i/o ov dd ? lcke am27 o ov dd ? lclk[0:2] an28, ak26, ap29 o ov dd ? lsync_out am12 o ov dd ? lsync_in aj10 i ov dd ? general purpose i/o timers gpio1[0]/dma_dreq0 /gtm1_tin1/ gtm2_tin2 f24 i/o ov dd ? gpio1[1]/dma_dack0 /gtm1_tgate1 / gtm2_tgate2 e24 i/o ov dd ? gpio1[2]/dma_ddone0 /gtm1_tout1 b25 i/o ov dd ? gpio1[3]/dma_dreq1 /gtm1_tin2/ gtm2_tin1 d24 i/o ov dd ? gpio1[4]/dma_dack1 /gtm1_tgate2 / gtm2_tgate1 a25 i/o ov dd ? gpio1[5]/dma_ddone1 /gtm1_tout2 / gtm2_tout1 b24 i/o ov dd ? gpio1[6]/dma_dreq2 /gtm1_tin3/ gtm2_tin4 a24 i/o ov dd ? gpio1[7]/dma_dack2 /gtm1_tgate3 / gtm2_tgate4 d23 i/o ov dd ? gpio1[8]/dma_ddone2 /gtm1_tout3 b23 i/o ov dd ? gpio1[9]/dma_dreq3 /gtm1_tin4/ gtm2_tin3 a23 i/o ov dd ? gpio1[10]/dma_dack3 /gtm1_tgate4 / gtm2_tgate3 f22 i/o ov dd ? gpio1[11]/dma_ddone3 /gtm1_tout4 / gtm2_tout3 e22 i/o ov dd ? usb port 1 mph1_d0_enablen/dr_d0_enablen a26 i/o ov dd ? mph1_d1_ser_txd/dr_ d1_ser_txd b26 i/o ov dd ? mph1_d2_vmo_se0/dr_d2_vmo_se0 d25 i/o ov dd ? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 62 freescale semiconductor package and pin listings mph1_d3_speed/dr_d3_speed a27 i/o ov dd ? mph1_d4_dp/dr_d4_dp b27 i/o ov dd ? mph1_d5_dm/dr_d5_dm c27 i/o ov dd ? mph1_d6_ser_rcv/dr_d6_ser_rcv d26 i/o ov dd ? mph1_d7_drvvbus/dr_d7_drvvbus e26 i/o ov dd ? mph1_nxt/dr_sess_vld_nxt d27 i ov dd ? mph1_dir_dppullup/ dr_xcvr_sel_dppullup a28 i/o ov dd ? mph1_stp_suspend/ dr_stp_suspend f26 o ov dd ? mph1_pwrfault/ dr_rx_error_pwrfault e27 i ov dd ? mph1_pctl0/dr_tx_valid_pctl0 a29 o ov dd ? mph1_pctl1/dr_tx_validh_pctl1 d28 o ov dd ? mph1_clk/dr_clk b29 i ov dd ? usb port 0 mph0_d0_enablen/ dr_d8_chgvbus c29 i/o ov dd ? mph0_d1_ser_txd/dr_d9_dchgvbus a30 i/o ov dd ? mph0_d2_vmo_se0/ dr_d10_dppd e28 i/o ov dd ? mph0_d3_speed/dr_d11_dmmd b30 i/o ov dd ? mph0_d4_dp/dr_d12_vbus_vld c30 i/o ov dd ? mph0_d5_dm/dr_d13_sess_end a31 i/o ov dd ? mph0_d6_ser_rcv/dr_d14 b31 i/o ov dd ? mph0_d7_drvvbus/dr_d15_idpullup c31 i/o ov dd ? mph0_nxt/dr_rx_active_id b32 i ov dd ? mph0_dir_dppullup/dr_reset a32 i/o ov dd ? mph0_stp_suspend/dr_tx_ready a33 i/o ov dd ? mph0_pwrfault/dr_rx_validh c32 i ov dd ? mph0_pctl0/dr_line_state0 d31 i/o ov dd ? mph0_pctl1/ dr_line_state1 e30 i/o ov dd ? mph0_clk/ dr_rx_valid b33 i ov dd ? programmable interrupt controller mcp_out an33 o ov dd 2 irq 0/mcp_in/ gpio2[12] c19 i/o ov dd ? irq [1:5]/gpio2[13:17] c22, a 22, d21, c21, b21 i/o ov dd ? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 63 package and pin listings irq [6]/gpio2[18]/ckstop_out a21 i/o ov dd ? irq [7]/gpio2[19]/ckstop_in c20 i/o ov dd ? ethernet management interface ec_mdc a7 o lv dd1 ? ec_mdio e9 i/o lv dd1 12 gigabit reference clock ec_gtx_clk125 c8 i lv dd1 ? three-speed ethernet contro ller (gigabit ethernet 1) tsec1_col/ gpio2[20] a17 i/o ov dd ? tsec1_crs/ gpio2[21] f12 i/o lv dd1 ? tsec1_gtx_clk d10 o lv dd1 3 tsec1_rx_clk a11 i lv dd1 ? tsec1_rx_dv b11 i lv dd1 ? tsec1_rx_er/ gpio2[26] b17 i/o ov dd ? tsec1_rxd[7:4]/ gpio2[22:25] b16, d16, e16, f16 i/o ov dd ? tsec1_rxd[3:0] e10, a8, f10, b8 i lv dd1 ? tsec1_tx_clk d17 i ov dd ? tsec1_txd[7:4]/ gpio2[27:30] a15, b15, a14, b14 i/o ov dd ? tsec1_txd[3:0] a10, e11, b10, a9 o lv dd1 11 tsec1_tx_en b9 o lv dd1 ? tsec1_tx_er/ gpio2[31] a16 i/o ov dd ? three-speed ethernet contro ller (gigabit ethernet 2) tsec2_col/ gpio1[21] c14 i/o ov dd ? tsec2_crs/ gpio1[22] d6 i/o lv dd2 ? tsec2_gtx_clk a4 o lv dd2 ? tsec2_rx_clk b4 i lv dd2 ? tsec2_rx_dv/ gpio1[23] e6 i/o lv dd2 ? tsec2_rxd[7:4]/ gpio1[26:29] a13, b13, c13, a12 i/o ov dd ? tsec2_rxd[3:0]/ gpio1[13:16] d7, a6, e8, b7 i/o lv dd2 ? tsec2_rx_er/ gpio1[25] d14 i/o ov dd ? tsec2_txd[7]/ gpio1[31] b12 i/o ov dd ? tsec2_txd[6]/dr_xcvr_term_sel c12 o ov dd ? tsec2_txd[5]/dr_utmi_opmode1 d12 o ov dd ? tsec2_txd[4]/dr_ut mi_opmode0 e12 o ov dd ? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 64 freescale semiconductor package and pin listings tsec2_txd[3:0]/gpio1[17:20] b5, a5, f8, b6 i/o lv dd2 ? tsec2_tx_er/ gpio1[24] f14 i/o ov dd ? tsec2_tx_en/ gpio1[12] c5 i/o lv dd2 3 tsec2_tx_clk/ gpio1[30] e14 i/o ov dd ? duart uart_sout[1:2]/ msrcid[0:1]/lsrcid[0:1] ak27, an29 o ov dd ? uart_sin[1:2]/ msrcid[2:3]/lsrcid[2:3] al28, am29 i/o ov dd ? uart_cts [1]/ msrcid4/lsrcid4 ap30 i/o ov dd ? uart_cts [2]/mdval/ ldval an30 i/o ov dd ? uart_rts [1:2] ap31, am30 o ov dd ? i 2 c interface iic1_sda ak29 i/o ov dd 2 iic1_scl ap32 i/o ov dd 2 iic2_sda an31 i/o ov dd 2 iic2_scl am31 i/o ov dd 2 spi spimosi/lcs [6] an32 i/o ov dd ? spimiso/lcs [7] ap33 i/o ov dd ? spiclk ak30 i/o ov dd ? spisel al31 i ov dd ? clocks pci_clk_out[0:2] an9, ap9, am10 o ov dd ? pci_clk_out[3]/lcs [6] an10 o ov dd ? pci_clk_out[4]/lcs [7] aj11 o ov dd ? pci_sync_in/pci_clock ak12 i ov dd ? pci_sync_out ap11 o ov dd 3 rtc/pit_clock am32 i ov dd ? clkin am9 i ov dd ? jtag tck e20 i ov dd ? tdi f20 i ov dd 4 tdo b20 o ov dd 3 tms a20 i ov dd 4 trst b19 i ov dd 4 table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 65 package and pin listings test test d22 i ov dd 6 test_sel al13 i ov dd 7 pmc quiesce a18 o ov dd ? system control poreset c18 i ov dd ? hreset b18 i/o ov dd 1 sreset d18 i/o ov dd 2 thermal management therm0 k32 i ? 9 power and ground signals av dd 1 l31 power for e300 pll (1.2 v) nominal, 1.3 v for 667 mhz) av dd 1? av dd 2 ap12 power for system pll (1.2 v) nominal, 1.3 v for 667 mhz) av dd 2? av dd 3 ae1 power for ddr dll (1.2 v) nominal, 1.3 v for 667 mhz) ?? av dd 4 aj13 power for lbiu dll (1.2 v) nominal, 1.3 v for 667 mhz) av dd 4? gnd a1, a34, c1, c7, c10, c11, c15, c23, c25, c28, d1, d8, d20, d30, e7, e13, e15, e17, e18, e21, e23, e25, e32, f6, f19, f27, f30, f34, g31, h5, j4, j34, k30, l5, m2, m5, m30, m33, n3, n5, p30, r5, r32, t5, t30, u6, u29, u33, v2, v5, v30, w6, w30, y30, aa2, aa30, ab2, ab6, ab30, ac3, ac6, ad31, ae5, af 2, af5, af31, ag30, ag31, ah4, aj3, aj19, aj22, ak7, ak13, ak14, ak16, ak18, ak20, ak25, ak28, al3, al5, al10, al12, al22, al27, am1, am6, am7, an12, an17, an34, ap1, ap8, ap34 ??? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 66 freescale semiconductor package and pin listings gv dd a2, e2, g5, g6, j5, k4, k5, l4, n4, p5, r6, t6, u5, v1, w5, y5, aa4, ab3, ac4, ad5, af3, ag5, ah2, ah5, ah6, aj6, ak6, ak8, ak9, al6 power for ddr dram i/o voltage (2.5 v) gv dd ? lv dd 1c9, d11power for three-speed ethernet #1 and for ethernet management interface i/o (2.5 v, 3.3 v) lv dd 1? lv dd 2 c6, d9 power for three-speed ethernet #2 i/o (2.5 v, 3.3 v) lv dd 2? v dd e19, e29, f7, f9, f1 1,f13, f15, f17, f18, f21, f23, f2 5, f29, h29, j6, k29, m29, n6, p29, t29, u30, v6, v29, w29, ab29, ac5, ad29, af6, af29, ah29, aj8, aj12, aj14, aj16, aj18, aj20, aj21, aj23, aj25, aj26, aj27, aj28, aj29, ak10 power for core (1.2 v nominal, 1.3 v for 667 mhz) v dd ? ov dd b22, b28, c16, c17, c24, c26, d13, d15, d19, d29, e31, f28, g33, h30, l29, l32, n32, p31, r31, u32, w31, y29, aa29, ac30, ae31, af30, ag29, aj17, aj30, ak11, al15, al19, al21, al29, al30, am20, am23, am24, am26, am28, an11, an13 pci, 10/100 ethernet, and other standard (3.3 v) ov dd ? mvref1 m3 i ddr reference voltage ? mvref2 ad2 i ddr reference voltage ? table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 67 package and pin listings table 56 provides the pinout listing for the mpc8347ea, 620 pbga package. no connection nc w32, aa31, aa32, aa33, aa34, ab31, ab32, ab33, ab34, ac29, ac31, ac33, ac34, ad30, ad32, ad33, ad34, ae29, ae30, ah32, ah33, ah34, am33, aj31, aj32, aj33, aj34, ak32, ak33, ak34, am34, al33, al34 , ak31, ah30, ac32, ae32, ah31, al32, ag34, ae33, af32, ae34, af34, af33, ag33, ag32, al11, am11, ap10, y32, y34, y31, y33 ??? notes: 1. this pin is an open-drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd . 2. this pin is an open-drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd . 3. during reset, this output is actively driven rather than three-stated. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull-up if the chip is in pci host mode. follow the pci specifications. 6. this pin must always be tied to gnd. 7. this pin must always be pulled up to ov dd . 8. this pin must always be left not connected. 9. thermal sensitive resistor. 10.it is recommended that mdic0 be tied to grd using an 18 resistor and mdic1 be tied to ddr power using an 18 resistor. 11.tsec1_txd[3] is required an external pull- up resistor. for proper functionality of the device, this pin must be pulled up or actively driven high during a hard reset. no external pull-down resistors are allowed to be attached to this net. 12. a weak pull-up resistor (2?10 k ) should be placed on this pin to lv dd1 . 13. for systems that boot from lo cal bus (gpcm)-control led nor flash, a pullu p on lgpl4 is required. table 56. mpc8347ea (pbga) pinout listing signal package pin number pin type power supply notes pci pci1_inta /irq_out d20 o ov dd 2 pci1_reset_out b21 o ov dd ? pci1_ad[31:0] e19, d17, a16, a18, b17, b16, d16, b18, e17, e16, a15, c16, d15, d14, c14, a12, d12, b11, c11, e12, a10, c10, a9, e11, e10, b9, b8, d9, a8, c9, d8, c8 i/o ov dd ? pci1_c/be [3:0] a17, a14, a11, b10 i/o ov dd ? pci1_par d13 i/o ov dd ? pci1_frame b14 i/o ov dd 5 table 55. mpc8347ea (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 68 freescale semiconductor package and pin listings pci1_trdy a13 i/o ov dd 5 pci1_irdy e13 i/o ov dd 5 pci1_stop c13 i/o ov dd 5 pci1_devsel b13 i/o ov dd 5 pci1_idsel c17 i ov dd ? pci1_serr c12 i/o ov dd 5 pci1_perr b12 i/o ov dd 5 pci1_req [0] a21 i/o ov dd pci1_req [1]/cpci1_hs_es c19 i ov dd ? pci1_req [2:4] c18, a19, e20 i ov dd ? pci1_gnt0 b20 i/o ov dd ? pci1_gnt1 /cpci1_hs_led c20 o ov dd ? pci1_gnt2 / cpci1_hs_enum b19 o ov dd ? pci1 _gnt [3:4] a20, e18 o ov dd ? m66en l26 i ov dd ? ddr sdram memory interface mdq[0:63] ac25, ad27, ad25, ah27, ae28, ad26, ad24, af27, af25, af28, ah24, ag26, ae25, ag25, ah26, ah25, ag22, ah22, ae21, ad19, ae22, af23, ae19, ag20, ag19, ad17, ae16, af16, af18, ag18, ah17, ah16, ag9, ad12, ag7, ae8, ad11, ah9, ah8, af6, af8, ae6, af1, ae4, ag8, ah3, ag3, ag4, ah2, ad7, ab4, ab3, ag1, ad5, ac2, ac1, ac4, aa3, y4, aa4, ab1, ab2, y5, y3 i/o gv dd ? mecc[0:4]/msrcid[0:4] ag13, ae14, ah12, ah10, ae15 i/o gv dd ? mecc[5]/mdval ah14 i/o gv dd ? mecc[6:7] ae13, ah11 i/o gv dd ? mdm[0:8] ag28, ag24, af20, ag17, ae9, ah5, ad1, aa2, ag12 ogv dd ? mdqs[0:8] ae27, ae26, ae2 0, ah18, ag10, af5, ac3, aa1, ah13 i/o gv dd ? mba[0:1] af10, af11 o gv dd ? ma[0:14] af13, af15, ag16, ad16, af17, ah20, ah19, ah21, ad18, ag21, ad13, af21, af22, ae1, aa5 ogv dd ? mwe ad10 o gv dd ? table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 69 package and pin listings mras af7 o gv dd ? mcas ag6 o gv dd ? mcs [0:3] ae7, ah7, ah4, af2 o gv dd ? mcke[0:1] ag23, ah23 o gv dd 3 mck[0:5] ah15, ae24, ae2, af14, ae23, ad3 o gv dd ? mck [0:5] ag15, ad23, ae3, ag14, af24, ad2 o gv dd ? modt[0:3] ag5, ad4, ah6, af4 o gv dd ? mba[2] ad22 o gv dd ? mdic0 ag11 i/o ? 9 mdic1 af12 i/o ? 9 local bus controller interface lad[0:31] t4, t5, t1, r2, r3, t2, r1, r4, p1, p2, p3, p4, n1, n4, n2 , n3, m1, m2, m3, n5, m4, l1, l2, l3, k1, m5, k2, k3, j1, j2, l5, j3 i/o ov dd ? ldp[0]/ckstop_out h1 i/o ov dd ? ldp[1]/ckstop_in k5 i/o ov dd ? ldp[2]/lcs [4] h2 i/o ov dd ? ldp[3]/lcs [5] g1 i/o ov dd ? la[27:31] j4, h3, g2, f1, g3 o ov dd ? lcs [0:3] j5, h4, f2, e1 o ov dd ? lwe [0:3]/lsddqm[0:3]/lbs [0:3] f3, g4, d1, e2 o ov dd ? lbctl h5 o ov dd ? lale e3 o ov dd ? lgpl0/lsda10/cfg_reset_source0 f4 i/o ov dd ? lgpl1/lsdwe/ cfg_reset_source1 d2 i/o ov dd ? lgpl2/lsdras /loe c1 o ov dd ? lgpl3/lsdcas /cfg_reset_source2 c2 i/o ov dd ? lgpl4/lgta /lupwait/lpbse c3 i/o ov dd 12 lgpl5/cfg_clkin_div b3 i/o ov dd ? lcke e4 o ov dd ? lclk[0:2] d4, a3, c4 o ov dd ? lsync_out u3 o ov dd ? lsync_in y2 i ov dd ? table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 70 freescale semiconductor package and pin listings general purpose i/o timers gpio1[0]/dma_dreq0 /gtm1_tin1/ gtm2_tin2 d27 i/o ov dd ? gpio1[1]/dma_dack0 /gtm1_tgate1 / gtm2_tgate2 e26 i/o ov dd ? gpio1[2]/dma_ddone0 /gtm1_tout1 d28 i/o ov dd ? gpio1[3]/dma_dreq1 /gtm1_tin2/ gtm2_tin1 g25 i/o ov dd ? gpio1[4]/dma_dack1 /gtm1_tgate2 / gtm2_tgate1 j24 i/o ov dd ? gpio1[5]/dma_ddone1 /gtm1_tout2 / gtm2_tout1 f26 i/o ov dd ? gpio1[6]/dma_dreq2 /gtm1_tin3/ gtm2_tin4 e27 i/o ov dd ? gpio1[7]/dma_dack2 /gtm1_tgate3 / gtm2_tgate4 e28 i/o ov dd ? gpio1[8]/dma_ddone2 /gtm1_tout3 h25 i/o ov dd ? gpio1[9]/dma_dreq3 /gtm1_tin4/ gtm2_tin3 f27 i/o ov dd ? gpio1[10]/dma_dack3 / gtm1_tgate4 /gtm2_tgate3 k24 i/o ov dd ? gpio1[11]/dma_ddone3 / gtm1_tout4 /gtm2_tout3 g26 i/o ov dd ? usb port 1 mph1_d0_enablen/dr_d0_enablen c28 i/o ov dd ? mph1_d1_ser_txd/dr_ d1_ser_txd f25 i/o ov dd ? mph1_d2_vmo_se0/dr_d2_vmo_se0 b28 i/o ov dd ? mph1_d3_speed/dr_d3_speed c27 i/o ov dd ? mph1_d4_dp/dr_d4_dp d26 i/o ov dd ? mph1_d5_dm/dr_d5_dm e25 i/o ov dd ? mph1_d6_ser_rcv/dr_d6_ser_rcv c26 i/o ov dd ? mph1_d7_drvvbus/dr_d7_drvvbus d25 i/o ov dd ? mph1_nxt/dr_sess_vld_nxt b26 i ov dd ? mph1_dir_dppullup/ dr_xcvr_sel_dppullup e24 i/o ov dd ? mph1_stp_suspend/ dr_stp_suspend a27 o ov dd ? mph1_pwrfault/ dr_rx_error_pwrfault c25 i ov dd ? table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 71 package and pin listings mph1_pctl0/dr_tx_valid_pctl0 a26 o ov dd ? mph1_pctl1/dr_tx_validh_pctl1 b25 o ov dd ? mph1_clk/dr_clk a25 i ov dd ? usb port 0 mph0_d0_enablen/ dr_d8_chgvbus d24 i/o ov dd ? mph0_d1_ser_txd/dr_d9_dchgvbus c24 i/o ov dd ? mph0_d2_vmo_se0/ dr_d10_dppd b24 i/o ov dd ? mph0_d3_speed/dr_d11_dmmd a24 i/o ov dd ? mph0_d4_dp/dr_d12_vbus_vld d23 i/o ov dd ? mph0_d5_dm/dr_d13_sess_end c23 i/o ov dd ? mph0_d6_ser_rcv/dr_d14 b23 i/o ov dd ? mph0_d7_drvvbus/dr_d15_idpullup a23 i/o ov dd ? mph0_nxt/dr_rx_active_id d22 i ov dd ? mph0_dir_dppullup/dr_reset c22 i/o ov dd ? mph0_stp_suspend/dr_tx_ready b22 i/o ov dd ? mph0_pwrfault/dr_rx_validh a22 i ov dd ? mph0_pctl0/dr_line_state0 e21 i/o ov dd ? mph0_pctl1/ dr_line_state1 d21 i/o ov dd ? mph0_clk/ dr_rx_valid c21 i ov dd ? programmable interrupt controller mcp_out e8 o ov dd 2 irq 0/mcp_in/ gpio2[12] j28 i/o ov dd ? irq [1:5]/gpio2[13:17] k25, j25, h26, l24, g27 i/o ov dd ? irq [6]/gpio2[18]/ckstop_out g28 i/o ov dd ? irq [7]/gpio2[19]/ckstop_in j26 i/o ov dd ? ethernet management interface ec_mdc y24 o lv dd1 ? ec_mdio y25 i/o lv dd1 11 gigabit reference clock ec_gtx_clk125 y26 i lv dd1 ? three-speed ethernet contro ller (gigabit ethernet 1) tsec1_col/ gpio2[20] m26 i/o ov dd ? tsec1_crs/ gpio2[21] u25 i/o lv dd1 ? tsec1_gtx_clk v24 o lv dd1 3 table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 72 freescale semiconductor package and pin listings tsec1_rx_clk u26 i lv dd1 ? tsec1_rx_dv u24 i lv dd1 ? tsec1_rx_er/ gpio2[26] l28 i/o ov dd ? tsec1_rxd[7:4]/ gpio2[22:25] m27, m28, n26, n27 i/o ov dd ? tsec1_rxd[3:0] w26, w24, y28, y27 i lv dd1 ? tsec1_tx_clk n25 i ov dd ? tsec1_txd[7:4]/ gpio2[27:30] n28, p25, p26, p27 i/o ov dd ? tsec1_txd[3:0] v28, v27, v26, w28 o lv dd1 10 tsec1_tx_en w27 o lv dd1 ? tsec1_tx_er/ gpio2[31] n24 i/o ov dd ? three-speed ethernet contro ller (gigabit ethernet 2) tsec2_col/ gpio1[21] p28 i/o ov dd ? tsec2_crs/ gpio1[22] ac28 i/o lv dd2 ? tsec2_gtx_clk ac27 o lv dd2 ? tsec2_rx_clk ab25 i lv dd2 ? tsec2_rx_dv/ gpio1[23] ac26 i/o lv dd2 ? tsec2_rxd[7:4]/ gpio1[26:29] r28, t24, t25, t26 i/o ov dd ? tsec2_rxd[3:0]/ gpio1[13:16] aa25, aa26, aa27, aa28 i/o lv dd2 ? tsec2_rx_er/ gpio1[25] r25 i/o ov dd ? tsec2_txd[7]/ gpio1[31] t27 i/o ov dd ? tsec2_txd[6]/dr_xcvr_term_sel t28 o ov dd ? tsec2_txd[5]/dr_utmi_opmode1 u28 o ov dd ? tsec2_txd[4]/dr_utmi_opmode0 u27 o ov dd ? tsec2_txd[3:0]/gpio1[17:20] ab26, ab27, aa24, ab28 i/o lv dd2 ? tsec2_tx_er/ gpio1[24] r27 i/o ov dd ? tsec2_tx_en/ gpio1[12] ad28 i/o lv dd2 3 tsec2_tx_clk/ gpio1[30] r26 i/o ov dd ? duart uart_sout[1:2]/ msrcid[0:1]/lsrcid[0:1] b4, a4 o ov dd ? uart_sin[1:2]/ msrcid[2:3]/lsrcid[2:3] d5, c5 i/o ov dd ? uart_cts [1]/ msrcid4/lsrcid4 b5 i/o ov dd ? uart_cts [2]/mdval/ldval a5 i/o ov dd ? uart_rts [1:2] d6, c6 o ov dd ? table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 73 package and pin listings i 2 c interface iic1_sda e5 i/o ov dd 2 iic1_scl a6 i/o ov dd 2 iic2_sda b6 i/o ov dd 2 iic2_scl e7 i/o ov dd 2 spi spimosi/lcs [6] d7 i/o ov dd ? spimiso/lcs [7] c7 i/o ov dd ? spiclk b7 i/o ov dd ? spisel a7 i ov dd ? clocks pci_clk_out[0:2] y1, w3, w2 o ov dd ? pci_clk_out[3]/lcs [6] w1 o ov dd ? pci_clk_out[4]/lcs [7] v3 o ov dd ? pci_sync_in/pci_clock u4 i ov dd ? pci_sync_out u5 o ov dd 3 rtc/pit_clock e9 i ov dd ? clkin w5 i ov dd ? jtag tck h27 i ov dd ? tdi h28 i ov dd 4 tdo m24 o ov dd 3 tms j27 i ov dd 4 trst k26 i ov dd 4 test test f28 i ov dd 6 test_sel t3 i ov dd 6 pmc quiesce k27 o ov dd ? system control poreset k28 i ov dd ? hreset m25 i/o ov dd 1 sreset l27 i/o ov dd 2 table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 74 freescale semiconductor package and pin listings thermal management therm0 b15 i ? 8 power and ground signals av dd 1 c15 power for e300 pll (1.2 v) nominal, 1.3 v for 667 mhz) av dd 1? av dd 2u1power for system pll (1.2 v) nominal, 1.3 v for 667 mhz) av dd 2? av dd 3 af9 power for ddr dll (1.2 v nominal, 1.3 v for 667 mhz) ? av dd 4u2power for lbiu dll (1.2 v nominal, 1.3 v for 667 mhz) av dd 4? gnd a2, b1, b2, d10, d18, e6, e14, e22, f9, f12, f15, f18, f21, f24, g5, h6, j23, l4, l6, l12, l13, l14, l15, l16, l17, m11, m12, m13, m14, m15, m16, m17, m18, m23, n11, n12, n13, n14, n15, n16, n17, n18, p6, p11, p12, p13, p14, p15, p16, p17, p18, p24, r5, r11, r12, r13, r14, r15, r16, r17, r18, r23, t11, t12, t13, t14, t15, t16, t17, t18, u6, u11, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v23, v25, w4, y6, aa23, ab24, ac5, ac8, ac11, ac14, ac17, ac20, ad9, ad15, ad21, ae12, ae18, af3, af26 ??? gv dd u9, v9, w10, w19, y11, y12, y14, y15, y17, y18, aa6, ab5, ac9, ac12, ac15, ac18, ac21, ac24, ad6, ad8, ad14, ad20, ae5, ae11, ae17, ag2, ag27 power for ddr dram i/o voltage (2.5 v) gv dd ? table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 75 package and pin listings lv dd 1 u20, w25 power for three-speed ethernet #1 and for ethernet management interface i/o (2.5 v, 3.3 v) lv dd 1? lv dd 2 v20, y23 power for three-speed ethernet #2 i/o (2.5 v, 3.3 v) lv dd 2? v dd j11, j12, j15, k10, k11, k12, k13, k14, k15, k16, k17, k18, k19, l10, l11, l18, l19, m10, m19, n10, n19, p9, p10, p19, r10, r19, r20, t10, t19, u10, u19, v10, v11, v18, v19, w11, w12, w13, w14, w15, w16, w17, w18 power for core (1.2 v) v dd ? ov dd b27, d3, d11, d19, e15, e23, f5, f8, f11, f14, f17, f20, g24, h23, h24, j6, j14, j17, j18, k4, l9, l20, l23, l25, m6, m9, m20, p5, p20, p23, r6, r9, r24, u23, v4, v6 pci, 10/100 ethernet, and other standard (3.3 v) ov dd ? mvref1 af19 i ddr reference voltage ? mvref2 ae10 i ddr reference voltage ? no connection nc v1, v2, v5 ? ? ? notes: 1. this pin is an open-drain signal. a weak pull-up resistor (1 k ) should be placed on this pin to ov dd . 2. this pin is an open-drain signal. a weak pull-up resistor (2?10 k ) should be placed on this pin to ov dd . 3. during reset, this output is actively driven rather than three-stated. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull-up if the chip is in pci host mode. follow the pci specifications. 6. this pin must always be tied to gnd. 7. this pin must always be left not connected. 8. thermal sensitive resistor. 9. it is recommended that mdic0 be tied to grd using an 18 resistor and mdic1 be tied to ddr power using an 18 resistor. 10.tsec1_txd[3] is required an external pull- up resistor. for proper functionality of the device, this pin must be pulled up or actively driven high during a hard reset. no external pull-down resistors are allowed to be attached to this net. 11. a weak pull-up resistor (2?10 k ) should be placed on this pin to lv dd1 . 12. for systems that boot from lo cal bus (gpcm)-control led nor flash, a pullu p on lgpl4 is required. table 56. mpc8347ea (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 76 freescale semiconductor clocking 19 clocking figure 42 shows the internal distribution of the clocks. figure 42. mpc8347ea clock subsystem the primary clock source can be one of two inputs, clkin or pci_clk, depe nding on whether the device is configured in pci host or pci agent mode. when the mpc8347ea is configur ed as a pci host device, clkin is its primary i nput clock. clkin feeds the pci clock divider ( 2) and the multiplexors for pci_sync_out and pci_clk_out. the cfg_clki n_div configuration i nput selects whether clkin or clkin/2 is driven out on th e pci_sync_out signal. the occr[pcicd n ] parameters select whether clkin or clkin/2 is driven out on the pci_clk_out n signals. pci_sync_out is connected externally to pci_sy nc_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system, to allow the mpc8347ea to function. when the device is configured as a pci agent device, pci_cl k is the primary input cl ock and the clkin signal should be tied to gnd. core pll system pll ddr lbiu lsync_in lsync_out lclk[0:2] mck[0:5] mck [0:5] core_clk e300 core csb_clk to rest clkin csb_clk 6 6 ddr memory local bus pci_clk_out[0:4] pci_sync_out pci_clk/ clock unit of the device ddr_clk lbiu_clk cfg_clkin_div pci clock pci_sync_in device memory device /n to local bus memory controller to d d r memory controller dll clock div /2 divider 5
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 77 clocking as shown in figure 42 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create the cohere nt system bus clock ( csb_clk ), the internal clock for the ddr controller ( ddr_clk ), and the internal clock for the local bus interface unit ( lbiu_clk ). the csb_clk frequency is derived from a co mplex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf in pci host mode, pci_sync_in (1 + cf g_clkin_div) is the clkin frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spm f and corepll fields in the rese t configuration word low (rcwl), which is loaded at power-on reset or by one of th e hard-coded reset options. see the chapter on reset, clocking, and initialization in the mpc8349ea reference manual for more information on the clock subsystem. the internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk (1 + rcwl[ddrcm]) ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( 2) to create the differential ddr memory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk (1 + rcwl[lbiucm]) lbiu_clk is not the external local bus frequency; lbiu_clk passes through the lbiu clock divider to create the external local bus clock outputs (lsync_out and lclk[0:2]). the lbiu clock divider ratio is controlled by lccr[clkdiv]. in addition, some of the internal units may have to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ratio that can be configured by a memory-mapped register after the device exits reset. table 57 specifies which units have a configurable clock frequency. table 58 provides the operating frequencies for the mpc8347ea tbga under recommended operating conditions (see table 2 ). all frequency combinations shown in the table below may not be available. maximum operating frequencies de pend on the part ordered, see section 22.1, ?part numbers fully table 57. configurable clock units unit default frequency options tsec1 csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 tsec2, i 2 c1 csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 security core csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 usb dr, usb mph csb_clk/3 off, csb_clk, csb_clk/2, csb_clk/3 pci and dma complex csb_clk off, csb_clk
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 78 freescale semiconductor clocking addressed by this document,? for part ordering details and contact your freescale sales representative or authorized distributor for more information. table 59 provides the operating frequencies for the mpc8347ea pbga under recommended operating conditions. table 58. operating frequencies for tbga characteristic 1 1 the clkin frequency, rcwl[spmf], an d rcwl[corepll] settings must be chosen so that the resulting csb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maxi mum or minimum operating frequencies. the value of sccr[enccm], sccr[usbdrcm], and sccr[usbmphcm] must be programmed so that the maximum internal operating frequency of the security core and usb modules does not exceed the respective values listed in this table. 400 mhz 533 mhz 667 mhz unit e300 core frequency ( core_clk ) 266?400 266?533 266?667 mhz coherent system bus frequency ( csb_clk ) 100?266 100?333 100?333 mhz ddr1 memory bus frequency (mck) 2 2 the ddr data rate is 2x the ddr memory bus frequency. 100?133 100?133 100?166.67 mhz ddr2 memory bus frequency (mck) 3 3 the ddr data rate is 2x the ddr memory bus frequency. 100?133 100?200 100?200 mhz local bus frequency (lclk n ) 4 4 the local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on lccr[clkdiv]) which is in turn 1x or 2x the csb_clk frequency (depending on rcwl[lbiucm]). 16.67?133 16.67?133 16.67?133 mhz pci input frequency (clkin or pci_clk) 25?66 25?66 25?66 mhz security core maximum internal operating frequency 133 133 166 mhz usb_dr, usb_mph maximum internal operating frequency 133 133 166 mhz table 59. operating frequencies for pbga parameter 1 1 the clkin frequency, rcwl[spmf], and rcwl[corepll] settings must be chosen so that the resulting csb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. the value of sccr[enccm], sccr[usbdrcm], and sccr[usbmphcm] must be programmed so that the maximum internal operating frequency of the security core and usb modules d oes not exceed the respective values listed in this table. 266 mhz 333 mhz 400 mhz unit e300 core frequency ( core_clk ) 200?266 200?333 200?400 mhz coherent system bus frequency ( csb_clk ) 100?266 mhz ddr1 memory bus frequency (mck) 2 2 the ddr data rate is 2 the ddr memory bus frequency. 100?133 mhz ddr2 memory bus frequency (mck) 3 100?133 mhz local bus frequency (lclk n ) 4 16.67?133 mhz pci input frequency (clkin or pci_clk) 25?66 mhz security core maximum internal operating frequency 133 mhz usb_dr, usb_mph maximum internal operating frequency 133 mhz
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 79 clocking 19.1 system pll configuration the system pll is controlled by the rcwl[spmf] parameter. table 60 shows the multiplication factor encodings for the system pll. as described in section 19, ?clocking,? the lbiucm, ddrcm, and spmf parameters in the reset configuration word low and the cf g_clkin_div configuration input si gnal select the ratio between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). table 61 3 the ddr data rate is 2 the ddr memory bus frequency. 4 the local bus frequency is ?, ?, or 1/8 of the lbiu_clk frequency (depending on lccr[clkdiv] ) which is in turn 1 or 2 the csb_clk frequency (depending on rcwl[lbiucm]). table 60. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 16 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 80 freescale semiconductor clocking and table 62 show the expected fre quency values for the cs b frequency for select csb_clk to clkin/pci_sync_in ratios. table 61. csb frequency options for host mode cfg_clkin_div at reset 1 1 cfg_clkin_div selects the ratio between clkin and pci_sync_out. spmf csb_clk : input clock ratio 2 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. ddr2 memory may be used at 133 mhz provided that the memo ry components are specified for operation at this frequency. input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2 : 1 133 low 0011 3 : 1 100 200 low 0100 4 : 1 100 133 266 low 0101 5 : 1 125 166 333 low 0110 6 : 1 100 150 200 low 0111 7 : 1 116 175 233 low 1000 8 : 1 133 200 266 low 1001 9 : 1 150 225 300 low 1010 10 : 1 166 250 333 low 1011 11 : 1 183 275 low 1100 12 : 1 200 300 low 1101 13 : 1 216 325 low 1110 14 : 1 233 low 1111 15 : 1 250 low 0000 16 : 1 266 high 0010 2 : 1 133 high 0011 3 : 1 100 200 high 0100 4 : 1 133 266 high 0101 5 : 1 166 333 high 0110 6 : 1 200 high 0111 7 : 1 233 high 1000 8 : 1
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 81 clocking 19.2 core pll configuration rcwl[corepll] selects the ratio between th e internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 63 shows the encodings for rcwl[cor epll]. corepll values that are not listed in table 63 should be considered as reserved. note core vco frequency = core frequency vco divider table 62. csb frequency options for agent mode cfg_clkin_div at reset 1 1 cfg_clkin_div doubles csb_clk if set high. spmf csb_clk : input clock ratio 2 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. ddr2 memory may be used at 133 mhz provided that the memo ry components are specified for operation at this frequency. input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2 : 1 133 low 0011 3 : 1 100 200 low 0100 4 : 1 100 133 266 low 0101 5 : 1 125 166 333 low 0110 6 : 1 100 150 200 low 0111 7 : 1 116 175 233 low 1000 8 : 1 133 200 266 low 1001 9 : 1 150 225 300 low 1010 10 : 1 166 250 333 low 1011 11 : 1 183 275 low 1100 12 : 1 200 300 low 1101 13 : 1 216 325 low 1110 14 : 1 233 low 1111 15 : 1 250 low 0000 16 : 1 266 high 0010 4 : 1 100 133 266 high 0011 6 : 1 100 150 200 high 0100 8 : 1 133 200 266 high 0101 10 : 1 166 250 333 high 0110 12 : 1 200 300 high 0111 14 : 1 233 high 1000 16 : 1 266
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 82 freescale semiconductor clocking vco divider must be set properly so th at the core vco frequency is in the range of 800?1800 mhz. table 63. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 1 1 core vco frequency = core frequency vco divider. the vco divider must be set properly so that the core vco frequency is in the range of 800?1800 mhz. 0?1 2?5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 83 clocking 19.3 suggested pll configurations table 64 shows suggested pll configurati ons for 33 and 66 mhz input clocks. table 64. suggested pll configurations ref no. 1 rcwl 400 mhz device 533 mhz device 667 mhz device spmf core pll input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) 33 mhz clkin/pci_clk options 922 1001 0100010 ?????f30033300300 723 0111 0100011 33 233 350 33 233 350 33 233 350 604 0110 0000100 33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100011 33 266 400 33 266 400 33 266 400 903 1001 0000011 ? 3330045033300450 923 1001 0100011 ? 3330045033300450 704 0111 0000011 ? 3323346633233466 724 0111 0100011 ? 3323346633233466 a03 1010 0000011 ? 33 333 500 33 333 500 804 1000 0000100 ? 3326653333266533 705 0111 0000101 ? ? 33 233 583 606 0110 0000110 ? ? 33 200 600 904 1001 0000100 ? ? 33 300 600 805 1000 0000101 ? ? 33 266 667 a04 1010 0000100 ? ? 33 333 667 66 mhz clkin/pci_clk options 304 0011 0000100 66 200 400 66 200 400 66 200 400 324 0011 0100100 66 200 400 66 200 400 66 200 400 403 0100 0000011 66 266 400 66 266 400 66 266 400 423 0100 0100011 66 266 400 66 266 400 66 266 400 305 0011 0000101 ? 6620050066200500 503 0101 0000011 ? 66 333 500 66 333 500 404 0100 0000100 ? 6626653366266533
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 84 freescale semiconductor thermal 20 thermal this section describes the thermal specifications of the mpc8347ea. 20.1 thermal characteristics table 65 provides the package therma l characteristics for the 672 35 35 mm tbga of the mpc8347ea. 306 0011 0000110 ? ? 66 200 600 405 0100 0000101 ? ? 66 266 667 504 0101 0000100 ? ? 66 333 667 1 the pll configuration reference number is the hexadecimal representation of rcwl, bits 4?15 associated with the spmf and corepll settings given in the table. 2 the input clock is clkin for pci host mode or pci_clk for pci agent mode. table 65. package thermal characteristics for tbga characteristic symbol value unit notes junction-to-ambient natural convection on single-layer board (1s) r ja 14 c/w 1, 2 junction-to-ambient natural convection on four-layer board (2s2p) r jma 11 c/w 1, 3 junction-to-ambient (at 200 ft/min) on single-layer board (1s) r jma 11 c/w 1, 3 junction-to-ambient (at 200 ft/min) on four-layer board (2s2p) r jma 8 c/w 1, 3 junction-to-ambient (at 2 m/s) on single-layer board (1s) r jma 9 c/w 1, 3 junction-to-ambient (at 2 m/s) on four-layer board (2s2p) r jma 7 c/w 1, 3 junction-to-board thermal r jb 3.8 c/w 4 junction-to-case thermal r jc 1.7 c/w 5 table 64. suggested pll configurations (continued) ref no. 1 rcwl 400 mhz device 533 mhz device 667 mhz device spmf core pll input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 85 thermal table 66 provides the package thermal characteristics for the 620 29 29 mm pbga of the mpc8347ea. 20.2 thermal management information for the following sections, p d = (v dd i dd ) + p i/o where p i/o is the power dissipati on of the i/o drivers. see table 5 for i/o power dissipation values. junction-to-package natural convection on top jt 1 c/w 6 notes: 1. junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 3. per jedec jesd51-6 with the board horizo ntal, 1 m/s is approximately equal to 200 linear feet per minute (lfm). 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, th e thermal characterization parameter is written as psi-jt. table 66. package thermal characteristics for pbga parameter symbol value unit notes junction-to-ambient natural convection on single-layer board (1s) r ja 21 c/w 1, 2 junction-to-ambient natural convection on four-layer board (2s2p) r jma 15 c/w 1, 3 junction-to-ambient (at 200 ft/min) on single-layer board (1s) r jma 17 c/w 1, 3 junction-to-ambient (at 200 ft/min) on four-layer board (2s2p) r jma 12 c/w 1, 3 junction-to-board thermal r jb 6 c/w 4 junction-to-case thermal r jc 5 c/w 5 junction-to-package natural convection on top jt 5 c/w 6 notes 1. junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, th e thermal characterization parameter is written as psi-jt. table 65. package thermal characteristics for tbga (continued) characteristic symbol value unit notes
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 86 freescale semiconductor thermal 20.2.1 estimation of junction temp erature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an i ndustry-standard value that provides a quick and easy estimation of thermal performance. generally, the value obtai ned on a single-layer boa rd is appropriate for a tightly packed printed-ci rcuit board. the value obtaine d on the board with the inte rnal planes is usually appropriate if the board has low pow er dissipation and the components are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j ?t a ) are possible. 20.2.2 estimation of junction te mperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. the thermal performan ce of any component is strongly de pendent on the power dissipation of surrounding components. in addition, the ambient temperature varies wi dely within the application. for many natural convection and especial ly closed box applications, the boa rd temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determ ine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t a + ( r ja p d ) where: t j = junction temperature ( c) t a = ambient temperature for the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the appli cation board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 87 thermal 20.2.3 experimental determinat ion of junction temperature to determine the junction temperatur e of the device in the application after prototypes ar e available, use the thermal characterization parameter ( jt ) to determine the junction temperature and a measure of the temperature at the top center of the p ackage case using the following equation: t j = t t + ( jt p d ) where: t j = junction temperature ( c) t t = thermocouple temperature on top of package ( c) jt = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the thermal characterizati on parameter is measured per the jesd51- 2 specification using a 40 gauge type t thermocouple epoxied to the top center of the p ackage case. the thermocoupl e should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 20.2.4 heat sinks and juncti on-to-case thermal resistance some application environments requi re a heat sink to provide the nece ssary thermal management of the device. when a heat sink is used, the thermal resist ance is expressed as the sum of a junction-to-case thermal resistance and a case-t o-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device-related and canno t be influenced by the us er. the user controls th e thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can ch ange the size of the heat sink, the air flow around the device, the interface material, the mounti ng arrangement on printed-circuit board, or change the thermal dissipation on th e printed-circuit board surrounding the device. the thermal performance of devices wi th heat sinks has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application e nvironment (tempera ture, air flow, adjacent component power dissipation) and the physical space available. because there is not a standard application environment, a sta ndard heat sink is not required.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 88 freescale semiconductor thermal table 67 and table 68 show heat sink thermal resistance for tbga and pbga of the mpc8347ea. f table 67. heat sink and thermal resistance of mpc8347ea (tbga) heat sink assuming thermal grease air flow 35 35 mm tbga thermal resistance aavid 30 30 9.4 mm pin fin natural convection 10 aavid 30 30 9.4 mm pin fin 1 m/s 6.5 aavid 30 30 9.4 mm pin fin 2 m/s 5.6 aavid 31 35 23 mm pin fin natural convection 8.4 aavid 31 35 23 mm pin fin 1 m/s 4.7 aavid 31 35 23 mm pin fin 2 m/s 4 wakefield, 53 53 25 mm pin fin natural convection 5.7 wakefield, 53 53 25 mm pin fin 1 m/s 3.5 wakefield, 53 53 25 mm pin fin 2 m/s 2.7 mei, 75 85 12 no adjacent board, extrusion natural convection 6.7 mei, 75 85 12 no adjacent board, extrusion 1 m/s 4.1 mei, 75 85 12 no adjacent board, extrusion 2 m/s 2.8 mei, 75 85 12 mm, adjacent board, 40 mm side bypass 1 m/s 3.1 table 68. heat sink and thermal resistance of mpc8347ea (pbga) heat sink assuming thermal grease air flow 29 29 mm pbga thermal resistance aavid 30 30 9.4 mm pin fin natural convection 13.5 aavid 30 30 9.4 mm pin fin 1 m/s 9.6 aavid 30 30 9.4 mm pin fin 2 m/s 8.8 aavid 31 35 23 mm pin fin natural convection 11.3 aavid 31 35 23 mm pin fin 1 m/s 8.1 aavid 31 35 23 mm pin fin 2 m/s 7.5 wakefield, 53 53 25 mm pin fin natural convection 9.1 wakefield, 53 53 25 mm pin fin 1 m/s 7.1 wakefield, 53 53 25 mm pin fin 2 m/s 6.5 mei, 75 85 12 no adjacent board, extrusion natural convection 10.1 mei, 75 85 12 no adjacent board, extrusion 1 m/s 7.7 mei, 75 85 12 no adjacent board, extrusion 2 m/s 6.6 mei, 75 85 12 mm, adjacent board, 40 mm side bypass 1 m/s 6.9
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 89 thermal accurate thermal design requires thermal modeling of the application environm ent using computational fluid dynamics software which can model both the conduction cooling a nd the convection cooling of the air moving through the application. si mplified thermal models of the pa ckages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in th e thermal resistance table. more detailed thermal models can be made available on request. heat sink vendors incl ude the following list: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-567-8082 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com international electronic resear ch corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electr onics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-2800 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendors include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials p.o. box 994 midland, mi 48686-0997 internet: www.dowcorning.com
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 90 freescale semiconductor thermal shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 20.3 heat sink attachment when heat sinks are attached, an in terface material is requi red, preferably thermal gr ease and a spring clip. the spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. avoid attachment fo rces that can lift the edge of the package or peel the package from the board. such peeling forces reduce the solder joint lifetime of the package. the recommended maximum force on the top of the package is 10 lb force (4.5 kg force). any adhesive attachment should attach to painte d or plastic surfaces, and its perfor mance should be verified under the application requirements. 20.3.1 experimental determination of the junction temperature with a heat sink when a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the in terface material. a clearance slot or hole is normally required in the heat sink. minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal inte rface to the heat sink. because of the experimental difficulties with this t echnique, many engineers measur e the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temp erature is determined from the j unction-to-case thermal resistance. t j = t c + ( r jc p d ) where: t j = junction temperature ( c) t c = case temperature of the package ( c) r jc = junction-to-case thermal resistance ( c/w) p d = power dissipation (w)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 91 system design information 21 system design information this section provides elect rical and thermal design r ecommendations for successf ul application of the mpc8347ea. 21.1 system clocking the mpc8347ea includes two plls: 1. the platform pll generates the platform cloc k from the externally supplied clkin input. the frequency ratio between the plat form and clkin is selected using the platform pll ratio configuration bits as described in section 19.1, ?system pll configuration.? 2. the e300 core pll generates the core clock as a slave to the platform clock. the frequency ratio between the e300 core clock and the platform clock is selected using the e300 pll ratio configuration bits as described in section 19.2, ?core pll configuration.? 21.2 pll power supply filtering each pll gets power through inde pendent power supply pins (av dd 1, av dd 2, respectively). the av dd level should always equal to v dd , and preferably these voltages are derived directly from v dd through a low frequency filter scheme. there are a number of ways to provi de power reliably to the plls, but the recommended solution is to provide four independent filter circuits as illustrated in figure 43 , one to each of the four av dd pins. independent filters to each pll reduce the opportunity to cause noise injection fr om one pll to the other. the circuit filters noise in the pll resonant frequency range from 500 k hz to 10 mhz. it should be built with surface mount capacitors with minimum effective series inducta nce (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are re commended over a single large value capacitor. to minimize noise coupled from near by circuits, each circuit should be pl aced as closely as possible to the specific av dd pin being supplied. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. figure 43 shows the pll power supply filter circuit. figure 43. pll power supply filter circuit 21.3 decoupling recommendations due to large address and data buses and high op erating frequencies, the mpc8347ea can generate transient power surges and high fr equency noise in its power supply , especially while driving large v dd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 92 freescale semiconductor system design information capacitive loads. this noise mu st be prevented from reaching ot her components in the mpc8347ea system, and the device itself requires a clean, tightly regulated sour ce of power. therefore, the system designer should place at least one decoupling capacitor at each v dd , ov dd , gv dd , and lv dd pin of the device. these capacitors should receive their pow er from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, with shor t traces to minimize inductance. capacitors can be placed directly under the device using a standard escape pa ttern. others can surround the part. these capacitors should have a va lue of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, distribute several bulk storag e capacitors around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smal ler chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick respons e time. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors are 100?330 f (avx tps tantalum or sanyo oscon). 21.4 connection recommendations to ensure reliable operation, connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc (no-connect ) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the mpc8347ea. 21.5 output buffer dc impedance the mpc8347ea drivers are characteri zed over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external re sistor is connected from the chip pad to ov dd or gnd. then the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 44 ). the output impedance is the av erage of two components, the resistances of the pul l-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 93 system design information ov dd /2. r p then becomes the resistan ce of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n ) 2. figure 44. driver impedance measurement two measurements give the value of th is resistance and the strength of th e driver current source. first, the output voltage is measured while driving logic 1 without an external differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is m easured while driving logic 1 with an external precision differenti al termination resistor of value r term . the measured voltage is v 2 =(1 (1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 v 2 ?1). the drive current is then i source =v 1 r source . table 69 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. 21.6 configuration pin multiplexing the mpc8347ea power-on configuration options ca n be set through extern al pull-up or pull-down resistors of 4.7 k on certain output pins (see the customer-visible conf iguration pins). these pins are used as output only pins in normal operation. table 69. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci signals (not including pci output clocks) pci output clocks (including pci_sync_out) ddr dram symbol unit r n 42 target 25 target 42 target 20 target z 0 w r p 42 target 25 target 42 target 20 target z 0 w differential na na na na z diff w note: nominal supply voltages. see ta b l e 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 94 freescale semiconductor ordering information however, while hreset is asserted, these pins are treated as i nputs, and the value on these pins is latched when poreset deasserts. then the input receiver is di sabled and the i/o circuit takes on its normal function. careful board layout with stubless connections to these pull-up/pull-down resist ors coupled with the large value of the pull-up/pull-dow n resistor should minimize the disr uption of signal qua lity or speed for the output pins. 21.7 pull-up resistor requirements the mpc8347ea requires high resi stance pull-up resistors (10 k is recommended) on open-drain pins, including i 2 c pins, and ipic interrupt pins. for more information on required pul l-up resistors and the connections required for the jtag interface, refer to application note an293 1, ?powerquicc design checklist.? 22 ordering information this section presents ordering information for the de vice discussed in this doc ument, and it shows an example of how the parts are marked. note the information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending in a or b). for information on revision 1.1 silic on and earlier versions, see the mpc8347e powerquicc ii pro integrated host processor hardware specifications (document order no. mpc8347eec). 22.1 part numbers fully ad dressed by this document table 70 shows an analysis of the freescale part numbering nomenclature for the mpc8347ea. the individual part numbers correspond to a maximum processor core fre quency. each part number also contains a revision code th at refers to the die mask revision numbe r. for available freq uency configuration
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 95 ordering information parts including extended temperatur es, refer to the device product summ ary page on our website listed on the back cover of this document or, c ontact your local frees cale sales office. table 71 shows the svr settings by device and package type. table 70. part numbering nomenclature mpc nnnn e t pp aa a r product code part identifier encryption acceleration temperature 1 range package 2 processor frequency 3 platform frequency revision level mpc 8347 blank = not included e = included blank = 0 to 105 c c = ?40 to 105 c zu =tbga vv = pb free tbga zq = pbga vr = pb free pbga e300 core speed ad = 266 ag = 400 aj = 533 al = 667 d = 266 f = 333 4 b = 3.1 notes: 1. for temperature range = c, processor frequency is limited to 400 (pbga) with a platform frequency of 266 and up to 533 (tbga) with a platform frequency of 333 2. see section 18, ?package and pin listings,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number spec ifications may support other maximum core frequencies. 4. alf marked parts support ddr1 data rate up to 333 mhz (at 333 mhz csb as the 'f' marking implies) and ddr2 data rate up to 400 mhz (at 200 mhz csb). ajf marked parts support ddr1 and ddr2 data rate up to 333 mhz (at a csb of 333 mhz). table 71. svr settings device package svr (rev. 3.0) mpc8347ea tbga 8052_0030 mpc8347a tbga 8053_0030 mpc8347ea pbga 8054_0030 mpc8347a pbga 8055_0030
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 96 freescale semiconductor document revision history 22.2 part marking parts are marked as in the example shown in figure 45 . figure 45. freescale part marking for tbga or pbga devices 23 document revision history this table provides a revision history of this document. table 72. document revision history rev. number date substantive change(s) 12 09/2011 ? in section 2.2, ?power sequencing ,? added section 2.2.1, ?power-up sequencing ? and figure 4 . ?in ta b l e 2 5 , ta b l e 2 9 and ta b l e 3 1 , removed the gtx_clk125. ?in ta b l e 3 4 , updated t mdkhdx max value from 170ns to 70ns. 11 11/2010 ? in ta b l e 5 6 , added overbar to lcs [4] and lcs [5] signals. in ta bl e 5 5 and ta bl e 5 6 , added note for pin lgpl4. ?in section 21.7, ?pull-up resistor requirements , updated the list of open drain type pins. 10 05/2010 ? in ta b l e 2 5 through ta b l e 3 0 , changed v il (min) to v ih (max) to (20%?80%). ? added ta b l e 8 , ?ec_gtx_clk125 ac timing specifications.? 9 5/2009 ? in section 18.3, ?package parameters for the mpc8347ea pbga , changed solder ball for tbga and pbga from 95.5 sn/0.5 cu/4 ag to 96.5 sn/3.5 ag. ?in ta b l e 5 8 , updated frequency for ddr2, from 100-200 to 100-133 at core frequency = 533mhz. ?in ta b l e 5 9 , added two columns for the ddr1 and ddr2 memory bus frequency. ?in ta bl e 7 0 , footnote 1, changed 667(tbga) to 533(tb ga). footnote 4, added data rate for ddr1 and ddr2. notes : atwlyyww is the traceability code. mpcnnnnetppaaar core/platform mhz atwlyyww ccccc tbga/ pbga *mmmmm ywwlaz ccccc is the country code. mmmmm is the mask number. ywwlaz is the assembly traceability code.
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 freescale semiconductor 97 document revision history 8 2/2009 ? added footnote 6 to ta b l e 7 . ?in section 9.2, ?usb ac electrical specifications ,? clarified that ac table is for ulpi only. ?in ta bl e 3 9 , corrected t lbkhov parameter to t lbklov (output data is driven on falling edge of clock in dll bypass mode). similarly, made the same correction to figure 22 , figure 24 , and figure 25 for output signals. ? added footnote 10 and 11 to ta b l e 5 5 and ta b l e 5 6 . ?in section 21.1, ?system clocking ,? removed ?(avdd1)? and ?(av dd2?) from bulleted list. ?in section 21.2, ?pll power supply filtering ,? in the second paragraph, changed ?provide five independent filter circuits,? and ?the five avdd pins ? to provide four independent filter circuits,? and ?the four avdd pins.? ?in ta b l e 5 8 , corrected the max csb_clk to 266 mhz. ?in ta b l e 6 4 , added pll configurations 903, 923, a03, a23, and 503 for 533 mhz ? added footnote 4 to ta b l e 7 0 . ?in ta b l e 7 0 , updated note 1 to say the following: ?for te mperature range = c, processor frequency is limited to 533 (tbga) and 400 (pbga) with a platform frequency of 266.? 7 4/2007 ? in ta b l e 3 , ?output drive capability,? changed the values in the output impedance column and added usb to the seventh row. ?in ta b l e 4 , ?operating frequencies for tbga,? added column for 400 mhz. ?in section 21.7, ?pull-up resistor requirements ,?deleted last two paragraphs and after first paragraph, added a new paragraph. ? deleted section 21.8, ?jtag configuration signa ls,? and figure 43, ?jtag interface connection.? 6 3/2007 ? page 1, updated first paragraph to reflect powerquicc ii pro information. ? in table 18, ?ddr and ddr2 sdram input ac timing specifications,? added note 2 to t ciskew and deleted original note 3; renumbered the remaining notes. ? in figure 43, ?jtag interface connection,? updated with new figure. ? in table 57, ?operating frequencies for tb ga,? in the ?coherent system bus frequency ( csb_clk )? row, changed the value in the 533 mhz column to 100-333. ? in table 63, ?suggested pll configurations ,? under the subhead, ?33 mhz clkin/pci_clk options,? added row a03 between ref. no. 724 and 804. under the subhead ?66 mhz clkin/pci_clk options,? added row 503 between ref. no. 305 and 404. for ref. no. 306, changed the core pll value to 0000110. ? in section 23, ?ordering information,? replaced first paragraph and added a note. ? in section 23.1, ?part numbers fully addresse d by this document,? replaced first paragraph. 5 1/2007 ? in table 1, ?absolute maximum ratings,? added (1.36 max for 667-mhz core frequency). ? in table 2, ?recommended operating conditions,? added a row showing nominal core supply voltage of 1.3 v for 667-mhz parts. ? in table 4, ?mpc8347ea power dissipation,? added two footnotes to 667-mhz row showing nominal core supply voltage of 1.3 v for 667-mhz parts. ? in table 54, ?mpc8347ea (tbga) pinout listing,? updated v dd row to show nominal core supply voltage of 1.3 v for 667-mhz parts. 4 12/2006 table 19, ?ddr and ddr2 sdram out put ac timing specifications,? modified t ddkhds for 333 mhz from 900 ps to 775 ps. 3 11/2006 ? updated note in introduction. ? in the features list in section 1, ?overview,? updated ddr data rate to show 266 mhz for pbga parts for all silicon revisions, and 400 mhz for ddr2 for tbga parts for silicon rev. 2 and 3. ? in table 5, ?mpc8347ea typical i/o power dissipation,? added gv dd 1.8-v values for ddr2; added table footnote to designate rates that apply only to the tbga package. ? in section 23, ?ordering information,? replicated note from document introduction. table 72. document revision history (continued) rev. number date substantive change(s)
mpc8347ea powerquicc ii pro integrated host processor hardware specifications, rev. 12 98 freescale semiconductor document revision history 2 8/2006 ? changed all references to revision 2.0 silicon to revision 3.0 silicon. ? changed vih minimum value in table 39, ?jtag interface dc electrical characteristics,? to ov dd ?0.3. ? in table 40, ?pci dc electrical characteristics,? changed high-level input voltage values to min = 2 and max = ov dd + 0.3; changed low-level input voltage values to min = (?0.3) and max = 0.8. ? in table 44, ?pci dc electrical characteristics,? changed high-level input voltage values to min = 2 and max = ov dd + 0.3; changed low-level input voltage values to min = (?0.3) and max = 0.8. ? updated ddr2 i/o power values in table 5, ?mpc8347ea typical i/o power dissipation.? ? in table 63, ?suggested pll configurations,? deleted reference-number rows 902 and 703. 1 4/2006 ? removed table 20, ?timing parameters for ddr2-400.? ? changed addr/cmd to addr/cmd/modt in table 9, ?ddr and ddr2 sdram output ac timing specifications,? rows 2 and 3, and in figure 2, ?ddr sdram output timing diagram. ? changed min and max values for v ih and vil in table 40,?pci dc electrical characteristics.? ? in table 51, ?mpc8347ea (tbga) pinout list ing,? and table 52, ?mpc8347ea (pbga) pinout listing,? modified rows for mdico and mdic 1 signals and added note ?it is recommended that mdico be tied to grd using an 18 resistor and mcic1 be tied to ddr power using an 18 resistor.? ? in table 51, ?mpc8347ea (tbga) pinout list ing,? and table 52, ?mpc8347ea (pbga) pinout listing,? in row avdd3 changed power supply from ?avdd3? to ??.? 0 3/2006 initial public release table 72. document revision history (continued) rev. number date substantive change(s)
document number: mpc8347eaec rev. 12 09/2011 information in this document is provid ed solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental da mages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or spec ifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale, the freescale logo and powerquicc are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2006?2011 freescale semiconductor, inc.

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